1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ 3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_ 4 5 #include <asm/page.h> 6 7 #ifndef __ASSEMBLY__ 8 /* 9 * Page size definition 10 * 11 * shift : is the "PAGE_SHIFT" value for that page size 12 * sllp : is a bit mask with the value of SLB L || LP to be or'ed 13 * directly to a slbmte "vsid" value 14 * penc : is the HPTE encoding mask for the "LP" field: 15 * 16 */ 17 struct mmu_psize_def { 18 unsigned int shift; /* number of bits */ 19 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ 20 unsigned int tlbiel; /* tlbiel supported for that page size */ 21 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ 22 union { 23 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ 24 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ 25 }; 26 }; 27 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 28 29 /* 30 * For BOOK3s 64 with 4k and 64K linux page size 31 * we want to use pointers, because the page table 32 * actually store pfn 33 */ 34 typedef pte_t *pgtable_t; 35 36 #endif /* __ASSEMBLY__ */ 37 38 /* 39 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS 40 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and 41 * page_to_nid does a page->section->node lookup 42 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce 43 * memory requirements with large number of sections. 44 * 51 bits is the max physical real address on POWER9 45 */ 46 #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \ 47 defined(CONFIG_PPC_64K_PAGES) 48 #define MAX_PHYSMEM_BITS 51 49 #else 50 #define MAX_PHYSMEM_BITS 46 51 #endif 52 53 /* 64-bit classic hash table MMU */ 54 #include <asm/book3s/64/mmu-hash.h> 55 56 #ifndef __ASSEMBLY__ 57 /* 58 * ISA 3.0 partition and process table entry format 59 */ 60 struct prtb_entry { 61 __be64 prtb0; 62 __be64 prtb1; 63 }; 64 extern struct prtb_entry *process_tb; 65 66 struct patb_entry { 67 __be64 patb0; 68 __be64 patb1; 69 }; 70 extern struct patb_entry *partition_tb; 71 72 /* Bits in patb0 field */ 73 #define PATB_HR (1UL << 63) 74 #define RPDB_MASK 0x0fffffffffffff00UL 75 #define RPDB_SHIFT (1UL << 8) 76 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */ 77 #define RTS1_MASK (3UL << RTS1_SHIFT) 78 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */ 79 #define RTS2_MASK (7UL << RTS2_SHIFT) 80 #define RPDS_MASK 0x1f /* root page dir. size field */ 81 82 /* Bits in patb1 field */ 83 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */ 84 #define PRTS_MASK 0x1f /* process table size field */ 85 #define PRTB_MASK 0x0ffffffffffff000UL 86 87 /* Number of supported PID bits */ 88 extern unsigned int mmu_pid_bits; 89 90 /* Base PID to allocate from */ 91 extern unsigned int mmu_base_pid; 92 93 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4) 94 #define PRTB_ENTRIES (1ul << mmu_pid_bits) 95 96 /* 97 * Power9 currently only support 64K partition table size. 98 */ 99 #define PATB_SIZE_SHIFT 16 100 101 typedef unsigned long mm_context_id_t; 102 struct spinlock; 103 104 /* Maximum possible number of NPUs in a system. */ 105 #define NV_MAX_NPUS 8 106 107 typedef struct { 108 union { 109 /* 110 * We use id as the PIDR content for radix. On hash we can use 111 * more than one id. The extended ids are used when we start 112 * having address above 512TB. We allocate one extended id 113 * for each 512TB. The new id is then used with the 49 bit 114 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits 115 * from EA and new context ids to build the new VAs. 116 */ 117 mm_context_id_t id; 118 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE]; 119 }; 120 121 /* Number of bits in the mm_cpumask */ 122 atomic_t active_cpus; 123 124 /* Number of users of the external (Nest) MMU */ 125 atomic_t copros; 126 127 /* NPU NMMU context */ 128 struct npu_context *npu_context; 129 struct hash_mm_context *hash_context; 130 131 unsigned long vdso_base; 132 /* 133 * pagetable fragment support 134 */ 135 void *pte_frag; 136 void *pmd_frag; 137 #ifdef CONFIG_SPAPR_TCE_IOMMU 138 struct list_head iommu_group_mem_list; 139 #endif 140 141 #ifdef CONFIG_PPC_MEM_KEYS 142 /* 143 * Each bit represents one protection key. 144 * bit set -> key allocated 145 * bit unset -> key available for allocation 146 */ 147 u32 pkey_allocation_map; 148 s16 execute_only_pkey; /* key holding execute-only protection */ 149 #endif 150 } mm_context_t; 151 152 static inline u16 mm_ctx_user_psize(mm_context_t *ctx) 153 { 154 return ctx->hash_context->user_psize; 155 } 156 157 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize) 158 { 159 ctx->hash_context->user_psize = user_psize; 160 } 161 162 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx) 163 { 164 return ctx->hash_context->low_slices_psize; 165 } 166 167 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx) 168 { 169 return ctx->hash_context->high_slices_psize; 170 } 171 172 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx) 173 { 174 return ctx->hash_context->slb_addr_limit; 175 } 176 177 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit) 178 { 179 ctx->hash_context->slb_addr_limit = limit; 180 } 181 182 #ifdef CONFIG_PPC_64K_PAGES 183 static inline struct slice_mask *mm_ctx_slice_mask_64k(mm_context_t *ctx) 184 { 185 return &ctx->hash_context->mask_64k; 186 } 187 #endif 188 189 static inline struct slice_mask *mm_ctx_slice_mask_4k(mm_context_t *ctx) 190 { 191 return &ctx->hash_context->mask_4k; 192 } 193 194 #ifdef CONFIG_HUGETLB_PAGE 195 static inline struct slice_mask *mm_ctx_slice_mask_16m(mm_context_t *ctx) 196 { 197 return &ctx->hash_context->mask_16m; 198 } 199 200 static inline struct slice_mask *mm_ctx_slice_mask_16g(mm_context_t *ctx) 201 { 202 return &ctx->hash_context->mask_16g; 203 } 204 #endif 205 206 #ifdef CONFIG_PPC_SUBPAGE_PROT 207 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx) 208 { 209 return ctx->hash_context->spt; 210 } 211 #endif 212 213 /* 214 * The current system page and segment sizes 215 */ 216 extern int mmu_linear_psize; 217 extern int mmu_virtual_psize; 218 extern int mmu_vmalloc_psize; 219 extern int mmu_vmemmap_psize; 220 extern int mmu_io_psize; 221 222 /* MMU initialization */ 223 void mmu_early_init_devtree(void); 224 void hash__early_init_devtree(void); 225 void radix__early_init_devtree(void); 226 extern void radix_init_native(void); 227 extern void hash__early_init_mmu(void); 228 extern void radix__early_init_mmu(void); 229 static inline void early_init_mmu(void) 230 { 231 if (radix_enabled()) 232 return radix__early_init_mmu(); 233 return hash__early_init_mmu(); 234 } 235 extern void hash__early_init_mmu_secondary(void); 236 extern void radix__early_init_mmu_secondary(void); 237 static inline void early_init_mmu_secondary(void) 238 { 239 if (radix_enabled()) 240 return radix__early_init_mmu_secondary(); 241 return hash__early_init_mmu_secondary(); 242 } 243 244 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 245 phys_addr_t first_memblock_size); 246 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, 247 phys_addr_t first_memblock_size); 248 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, 249 phys_addr_t first_memblock_size) 250 { 251 if (early_radix_enabled()) 252 return radix__setup_initial_memory_limit(first_memblock_base, 253 first_memblock_size); 254 return hash__setup_initial_memory_limit(first_memblock_base, 255 first_memblock_size); 256 } 257 258 extern int (*register_process_table)(unsigned long base, unsigned long page_size, 259 unsigned long tbl_size); 260 261 #ifdef CONFIG_PPC_PSERIES 262 extern void radix_init_pseries(void); 263 #else 264 static inline void radix_init_pseries(void) { }; 265 #endif 266 267 static inline int get_user_context(mm_context_t *ctx, unsigned long ea) 268 { 269 int index = ea >> MAX_EA_BITS_PER_CONTEXT; 270 271 if (likely(index < ARRAY_SIZE(ctx->extended_id))) 272 return ctx->extended_id[index]; 273 274 /* should never happen */ 275 WARN_ON(1); 276 return 0; 277 } 278 279 static inline unsigned long get_user_vsid(mm_context_t *ctx, 280 unsigned long ea, int ssize) 281 { 282 unsigned long context = get_user_context(ctx, ea); 283 284 return get_vsid(context, ea, ssize); 285 } 286 287 #endif /* __ASSEMBLY__ */ 288 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ 289