xref: /linux/arch/powerpc/boot/dts/turris1x.dts (revision fc6dfd5547794b0bf10790576a9d97443d975439) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Turris 1.x Device Tree Source
4 *
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
6 *
7 * Pinout, Schematics and Altium hardware design files are open source
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/leds/common.h>
14/include/ "fsl/p2020si-pre.dtsi"
15
16/ {
17	model = "Turris 1.x";
18	compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		ethernet2 = &enet2;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		pci0 = &pci0;
27		pci1 = &pci1;
28		pci2 = &pci2;
29		spi0 = &spi0;
30	};
31
32	memory {
33		device_type = "memory";
34	};
35
36	soc: soc@ffe00000 {
37		ranges = <0x0 0x0 0xffe00000 0x00100000>;
38
39		i2c@3000 {
40			/* PCA9557PW GPIO controller for boot config */
41			gpio-controller@18 {
42				compatible = "nxp,pca9557";
43				label = "bootcfg";
44				reg = <0x18>;
45				#gpio-cells = <2>;
46				gpio-controller;
47				polarity = <0x00>;
48			};
49
50			/* STM32F030R8T6 MCU for power control */
51			power-control@2a {
52				/*
53				 * Turris Power Control firmware runs on STM32F0 MCU.
54				 * This firmware is open source and available at:
55				 * https://gitlab.nic.cz/turris/hw/turris_power_control
56				 */
57				reg = <0x2a>;
58			};
59
60			/* DDR3 SPD/EEPROM PSWP instruction */
61			eeprom@32 {
62				reg = <0x32>;
63			};
64
65			/* SA56004ED temperature control */
66			temperature-sensor@4c {
67				compatible = "nxp,sa56004";
68				reg = <0x4c>;
69				interrupt-parent = <&gpio>;
70				interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
71					     <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
72			};
73
74			/* DDR3 SPD/EEPROM */
75			eeprom@52 {
76				compatible = "atmel,spd";
77				reg = <0x52>;
78			};
79
80			/* MCP79402-I/ST Protected EEPROM */
81			eeprom@57 {
82				reg = <0x57>;
83			};
84
85			/* ATSHA204-TH-DA-T crypto module */
86			crypto@64 {
87				compatible = "atmel,atsha204";
88				reg = <0x64>;
89			};
90
91			/* IDT6V49205BNLGI clock generator */
92			clock-generator@69 {
93				compatible = "idt,6v49205b";
94				reg = <0x69>;
95			};
96
97			/* MCP79402-I/ST RTC */
98			rtc@6f {
99				compatible = "microchip,mcp7940x";
100				reg = <0x6f>;
101				interrupt-parent = <&gpio>;
102				interrupts = <14 0>; /* GPIO14 - MFP pin */
103			};
104		};
105
106		/* SPI on connector P1 */
107		spi0: spi@7000 {
108		};
109
110		gpio: gpio-controller@fc00 {
111			#interrupt-cells = <2>;
112			interrupt-controller;
113		};
114
115		/* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
116		usb@22000 {
117			phy_type = "ulpi";
118			dr_mode = "host";
119		};
120
121		enet0: ethernet@24000 {
122			/* Connected to port 6 of QCA8337N-AL3C switch */
123			phy-connection-type = "rgmii-id";
124
125			fixed-link {
126				speed = <1000>;
127				full-duplex;
128			};
129		};
130
131		mdio@24520 {
132			/* KSZ9031RNXCA ethernet phy for WAN port */
133			phy: ethernet-phy@7 {
134				interrupts = <3 1 0 0>;
135				reg = <0x7>;
136			};
137
138			/* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
139			switch@10 {
140				compatible = "qca,qca8337";
141				interrupts = <2 1 0 0>;
142				reg = <0x10>;
143
144				ports {
145					#address-cells = <1>;
146					#size-cells = <0>;
147
148					port@0 {
149						reg = <0>;
150						label = "cpu";
151						ethernet = <&enet1>;
152						phy-mode = "rgmii-id";
153
154						fixed-link {
155							speed = <1000>;
156							full-duplex;
157						};
158					};
159
160					port@1 {
161						reg = <1>;
162						label = "lan5";
163					};
164
165					port@2 {
166						reg = <2>;
167						label = "lan4";
168					};
169
170					port@3 {
171						reg = <3>;
172						label = "lan3";
173					};
174
175					port@4 {
176						reg = <4>;
177						label = "lan2";
178					};
179
180					port@5 {
181						reg = <5>;
182						label = "lan1";
183					};
184
185					port@6 {
186						reg = <6>;
187						label = "cpu";
188						ethernet = <&enet0>;
189						phy-mode = "rgmii-id";
190
191						fixed-link {
192							speed = <1000>;
193							full-duplex;
194						};
195					};
196				};
197			};
198		};
199
200		ptp_clock@24e00 {
201			fsl,tclk-period = <5>;
202			fsl,tmr-prsc = <200>;
203			fsl,tmr-add = <0xcccccccd>;
204			fsl,tmr-fiper1 = <0x3b9ac9fb>;
205			fsl,tmr-fiper2 = <0x0001869b>;
206			fsl,max-adj = <249999999>;
207		};
208
209		enet1: ethernet@25000 {
210			/* Connected to port 0 of QCA8337N-AL3C switch */
211			phy-connection-type = "rgmii-id";
212
213			fixed-link {
214				speed = <1000>;
215				full-duplex;
216			};
217		};
218
219		mdio@25520 {
220			status = "disabled";
221		};
222
223		enet2: ethernet@26000 {
224			/* Connected to KSZ9031RNXCA ethernet phy (WAN port) */
225			label = "wan";
226			phy-handle = <&phy>;
227			phy-connection-type = "rgmii-id";
228		};
229
230		mdio@26520 {
231			status = "disabled";
232		};
233
234		sdhc@2e000 {
235			bus-width = <4>;
236			cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
237		};
238	};
239
240	lbc: localbus@ffe05000 {
241		reg = <0 0xffe05000 0 0x1000>;
242
243		ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */
244			 <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */
245			 <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */
246
247		/* S29GL128P90TFIR10 NOR */
248		nor@0,0 {
249			compatible = "cfi-flash";
250			reg = <0x0 0x0 0x01000000>;
251			bank-width = <2>;
252			device-width = <1>;
253
254			partitions {
255				compatible = "fixed-partitions";
256				#address-cells = <1>;
257				#size-cells = <1>;
258
259				partition@0 {
260					/* 128 kB for Device Tree Blob */
261					reg = <0x00000000 0x00020000>;
262					label = "dtb";
263				};
264
265				partition@20000 {
266					/* 1.7 MB for Linux Kernel Image */
267					reg = <0x00020000 0x001a0000>;
268					label = "kernel";
269				};
270
271				partition@1c0000 {
272					/* 1.5 MB for Rescue JFFS2 Root File System */
273					reg = <0x001c0000 0x00180000>;
274					label = "rescue";
275				};
276
277				partition@340000 {
278					/* 11 MB for TAR.XZ Archive with Factory content of NAND Root File System */
279					reg = <0x00340000 0x00b00000>;
280					label = "factory";
281				};
282
283				partition@e40000 {
284					/* 768 kB for Certificates JFFS2 File System */
285					reg = <0x00e40000 0x000c0000>;
286					label = "certificates";
287				};
288
289				/* free unused space 0x00f00000-0x00f20000 */
290
291				partition@f20000 {
292					/* 128 kB for U-Boot Environment Variables */
293					reg = <0x00f20000 0x00020000>;
294					label = "u-boot-env";
295				};
296
297				partition@f40000 {
298					/* 768 kB for U-Boot Bootloader Image */
299					reg = <0x00f40000 0x000c0000>;
300					label = "u-boot";
301				};
302			};
303		};
304
305		/* MT29F2G08ABAEAWP:E NAND */
306		nand@1,0 {
307			compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
308			reg = <0x1 0x0 0x00040000>;
309			nand-ecc-mode = "soft";
310			nand-ecc-algo = "bch";
311
312			partitions {
313				compatible = "fixed-partitions";
314				#address-cells = <1>;
315				#size-cells = <1>;
316
317				partition@0 {
318					/* 256 MB for UBI with one volume: UBIFS Root File System */
319					reg = <0x00000000 0x10000000>;
320					label = "rootfs";
321				};
322			};
323		};
324
325		/* LCMXO1200C-3FTN256C FPGA */
326		cpld@3,0 {
327			/*
328			 * Turris CPLD firmware which runs on this Lattice FPGA,
329			 * is extended version of P1021RDB-PC CPLD v4.1 firmware.
330			 * It is backward compatible with its original version
331			 * and the only extension is support for Turris LEDs.
332			 * Turris CPLD firmware is open source and available at:
333			 * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
334			 */
335			compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
336			reg = <0x3 0x0 0x30>;
337			#address-cells = <1>;
338			#size-cells = <1>;
339			ranges = <0x0 0x3 0x0 0x00020000>;
340
341			/* MAX6370KA+T watchdog */
342			watchdog@2 {
343				/*
344				 * CPLD firmware maps SET0, SET1 and SET2
345				 * input logic of MAX6370KA+T chip to CPLD
346				 * memory space at byte offset 0x2. WDI
347				 * input logic is outside of the CPLD and
348				 * connected via external GPIO.
349				 */
350				compatible = "maxim,max6370";
351				reg = <0x02 0x01>;
352				gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
353			};
354
355			reboot@d {
356				compatible = "syscon-reboot";
357				reg = <0x0d 0x01>;
358				offset = <0x0d>;
359				mask = <0x01>;
360				value = <0x01>;
361			};
362
363			led-controller@13 {
364				/*
365				 * LEDs are controlled by CPLD firmware.
366				 * All five LAN LEDs share common RGB settings
367				 * and so it is not possible to set different
368				 * colors on different LAN ports.
369				 */
370				compatible = "cznic,turris1x-leds";
371				reg = <0x13 0x1d>;
372				#address-cells = <1>;
373				#size-cells = <0>;
374
375				multi-led@0 {
376					reg = <0x0>;
377					color = <LED_COLOR_ID_RGB>;
378					function = LED_FUNCTION_WAN;
379				};
380
381				multi-led@1 {
382					reg = <0x1>;
383					color = <LED_COLOR_ID_RGB>;
384					function = LED_FUNCTION_LAN;
385					function-enumerator = <5>;
386				};
387
388				multi-led@2 {
389					reg = <0x2>;
390					color = <LED_COLOR_ID_RGB>;
391					function = LED_FUNCTION_LAN;
392					function-enumerator = <4>;
393				};
394
395				multi-led@3 {
396					reg = <0x3>;
397					color = <LED_COLOR_ID_RGB>;
398					function = LED_FUNCTION_LAN;
399					function-enumerator = <3>;
400				};
401
402				multi-led@4 {
403					reg = <0x4>;
404					color = <LED_COLOR_ID_RGB>;
405					function = LED_FUNCTION_LAN;
406					function-enumerator = <2>;
407				};
408
409				multi-led@5 {
410					reg = <0x5>;
411					color = <LED_COLOR_ID_RGB>;
412					function = LED_FUNCTION_LAN;
413					function-enumerator = <1>;
414				};
415
416				multi-led@6 {
417					reg = <0x6>;
418					color = <LED_COLOR_ID_RGB>;
419					function = LED_FUNCTION_WLAN;
420				};
421
422				multi-led@7 {
423					reg = <0x7>;
424					color = <LED_COLOR_ID_RGB>;
425					function = LED_FUNCTION_POWER;
426				};
427			};
428		};
429	};
430
431	pci2: pcie@ffe08000 {
432		/*
433		 * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
434		 * This xHCI controller is available only on Turris 1.1 boards.
435		 * Turris 1.0 boards have nothing connected to this PCIe bus,
436		 * so system would see only PCIe Root Port of this PCIe Root
437		 * Complex. TUSB7340RKM xHCI controller has four SuperSpeed
438		 * channels. Channel 0 is connected to the front USB 3.0 port,
439		 * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
440		 * slot 1 (CN5), channels 2 and 3 to connector P600.
441		 *
442		 * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller
443		 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
444		 * So allocate 2MB of PCIe MEM for this PCIe bus.
445		 */
446		reg = <0 0xffe08000 0 0x1000>;
447		ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */
448			 <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
449
450		pcie@0 {
451			ranges;
452		};
453	};
454
455	pci1: pcie@ffe09000 {
456		/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
457		reg = <0 0xffe09000 0 0x1000>;
458		ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */
459			 <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */
460
461		pcie@0 {
462			ranges;
463		};
464	};
465
466	pci0: pcie@ffe0a000 {
467		/*
468		 * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
469		 * Turris 1.1 boards have in this mPCIe slot additional USB 2.0
470		 * pins via channel 1 of TUSB7340RKM xHCI controller and also
471		 * additional SIM card slot, both for USB-based WWAN cards.
472		 */
473		reg = <0 0xffe0a000 0 0x1000>;
474		ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */
475			 <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */
476
477		pcie@0 {
478			ranges;
479		};
480	};
481};
482
483/include/ "fsl/p2020si-post.dtsi"
484