1/* 2 * TQM5200 board Device Tree Source 3 * 4 * Copyright (C) 2007 Semihalf 5 * Marian Balakowicz <m8@semihalf.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 interrupt-parent = <&mpc5200_pic>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 PowerPC,5200@0 { 27 device_type = "cpu"; 28 reg = <0>; 29 d-cache-line-size = <32>; 30 i-cache-line-size = <32>; 31 d-cache-size = <0x4000>; // L1, 16K 32 i-cache-size = <0x4000>; // L1, 16K 33 timebase-frequency = <0>; // from bootloader 34 bus-frequency = <0>; // from bootloader 35 clock-frequency = <0>; // from bootloader 36 }; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x00000000 0x04000000>; // 64MB 42 }; 43 44 soc5200@f0000000 { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 compatible = "fsl,mpc5200-immr"; 48 ranges = <0 0xf0000000 0x0000c000>; 49 reg = <0xf0000000 0x00000100>; 50 bus-frequency = <0>; // from bootloader 51 system-frequency = <0>; // from bootloader 52 53 cdm@200 { 54 compatible = "fsl,mpc5200-cdm"; 55 reg = <0x200 0x38>; 56 }; 57 58 mpc5200_pic: interrupt-controller@500 { 59 // 5200 interrupts are encoded into two levels; 60 interrupt-controller; 61 #interrupt-cells = <3>; 62 compatible = "fsl,mpc5200-pic"; 63 reg = <0x500 0x80>; 64 }; 65 66 timer@600 { // General Purpose Timer 67 compatible = "fsl,mpc5200-gpt"; 68 reg = <0x600 0x10>; 69 interrupts = <1 9 0>; 70 fsl,has-wdt; 71 }; 72 73 can@900 { 74 compatible = "fsl,mpc5200-mscan"; 75 interrupts = <2 17 0>; 76 reg = <0x900 0x80>; 77 }; 78 79 can@980 { 80 compatible = "fsl,mpc5200-mscan"; 81 interrupts = <2 18 0>; 82 reg = <0x980 0x80>; 83 }; 84 85 gpio_simple: gpio@b00 { 86 compatible = "fsl,mpc5200-gpio"; 87 reg = <0xb00 0x40>; 88 interrupts = <1 7 0>; 89 gpio-controller; 90 #gpio-cells = <2>; 91 }; 92 93 usb@1000 { 94 compatible = "fsl,mpc5200-ohci","ohci-be"; 95 reg = <0x1000 0xff>; 96 interrupts = <2 6 0>; 97 }; 98 99 dma-controller@1200 { 100 compatible = "fsl,mpc5200-bestcomm"; 101 reg = <0x1200 0x80>; 102 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 103 3 4 0 3 5 0 3 6 0 3 7 0 104 3 8 0 3 9 0 3 10 0 3 11 0 105 3 12 0 3 13 0 3 14 0 3 15 0>; 106 }; 107 108 xlb@1f00 { 109 compatible = "fsl,mpc5200-xlb"; 110 reg = <0x1f00 0x100>; 111 }; 112 113 serial@2000 { // PSC1 114 compatible = "fsl,mpc5200-psc-uart"; 115 reg = <0x2000 0x100>; 116 interrupts = <2 1 0>; 117 }; 118 119 serial@2200 { // PSC2 120 compatible = "fsl,mpc5200-psc-uart"; 121 reg = <0x2200 0x100>; 122 interrupts = <2 2 0>; 123 }; 124 125 serial@2400 { // PSC3 126 compatible = "fsl,mpc5200-psc-uart"; 127 reg = <0x2400 0x100>; 128 interrupts = <2 3 0>; 129 }; 130 131 ethernet@3000 { 132 compatible = "fsl,mpc5200-fec"; 133 reg = <0x3000 0x400>; 134 local-mac-address = [ 00 00 00 00 00 00 ]; 135 interrupts = <2 5 0>; 136 phy-handle = <&phy0>; 137 }; 138 139 mdio@3000 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "fsl,mpc5200-mdio"; 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 145 146 phy0: ethernet-phy@0 { 147 reg = <0>; 148 }; 149 }; 150 151 ata@3a00 { 152 compatible = "fsl,mpc5200-ata"; 153 reg = <0x3a00 0x100>; 154 interrupts = <2 7 0>; 155 }; 156 157 i2c@3d40 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 161 reg = <0x3d40 0x40>; 162 interrupts = <2 16 0>; 163 164 rtc@68 { 165 compatible = "dallas,ds1307"; 166 reg = <0x68>; 167 }; 168 }; 169 170 sram@8000 { 171 compatible = "fsl,mpc5200-sram"; 172 reg = <0x8000 0x4000>; 173 }; 174 }; 175 176 localbus { 177 compatible = "fsl,mpc5200-lpb","simple-bus"; 178 #address-cells = <2>; 179 #size-cells = <1>; 180 ranges = <0 0 0xfc000000 0x02000000>; 181 182 flash@0,0 { 183 compatible = "cfi-flash"; 184 reg = <0 0 0x02000000>; 185 bank-width = <4>; 186 device-width = <2>; 187 #size-cells = <1>; 188 #address-cells = <1>; 189 }; 190 }; 191 192 pci@f0000d00 { 193 #interrupt-cells = <1>; 194 #size-cells = <2>; 195 #address-cells = <3>; 196 device_type = "pci"; 197 compatible = "fsl,mpc5200-pci"; 198 reg = <0xf0000d00 0x100>; 199 interrupt-map-mask = <0xf800 0 0 7>; 200 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 201 0xc000 0 0 2 &mpc5200_pic 0 0 3 202 0xc000 0 0 3 &mpc5200_pic 0 0 3 203 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 204 clock-frequency = <0>; // From boot loader 205 interrupts = <2 8 0 2 9 0 2 10 0>; 206 bus-range = <0 0>; 207 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 208 0x02000000 0 0x90000000 0x90000000 0 0x10000000 209 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 210 }; 211}; 212