1/* 2 * STX GP3 - 8560 ADS Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "stx,gp3"; 16 compatible = "stx,gp3-8560", "stx,gp3"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 pci0 = &pci0; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8560@0 { 32 device_type = "cpu"; 33 reg = <0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <32768>; 37 i-cache-size = <32768>; 38 timebase-frequency = <0>; 39 bus-frequency = <0>; 40 clock-frequency = <0>; 41 next-level-cache = <&L2>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x10000000>; 48 }; 49 50 soc@fdf00000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 device_type = "soc"; 54 ranges = <0 0xfdf00000 0x100000>; 55 bus-frequency = <0>; 56 compatible = "fsl,mpc8560-immr", "simple-bus"; 57 58 ecm-law@0 { 59 compatible = "fsl,ecm-law"; 60 reg = <0x0 0x1000>; 61 fsl,num-laws = <8>; 62 }; 63 64 ecm@1000 { 65 compatible = "fsl,mpc8560-ecm", "fsl,ecm"; 66 reg = <0x1000 0x1000>; 67 interrupts = <17 2>; 68 interrupt-parent = <&mpic>; 69 }; 70 71 memory-controller@2000 { 72 compatible = "fsl,mpc8540-memory-controller"; 73 reg = <0x2000 0x1000>; 74 interrupt-parent = <&mpic>; 75 interrupts = <18 2>; 76 }; 77 78 L2: l2-cache-controller@20000 { 79 compatible = "fsl,mpc8540-l2-cache-controller"; 80 reg = <0x20000 0x1000>; 81 cache-line-size = <32>; 82 cache-size = <0x40000>; // L2, 256K 83 interrupt-parent = <&mpic>; 84 interrupts = <16 2>; 85 }; 86 87 i2c@3000 { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 cell-index = <0>; 91 compatible = "fsl-i2c"; 92 reg = <0x3000 0x100>; 93 interrupts = <43 2>; 94 interrupt-parent = <&mpic>; 95 dfsrr; 96 }; 97 98 dma@21300 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; 102 reg = <0x21300 0x4>; 103 ranges = <0x0 0x21100 0x200>; 104 cell-index = <0>; 105 dma-channel@0 { 106 compatible = "fsl,mpc8560-dma-channel", 107 "fsl,eloplus-dma-channel"; 108 reg = <0x0 0x80>; 109 cell-index = <0>; 110 interrupt-parent = <&mpic>; 111 interrupts = <20 2>; 112 }; 113 dma-channel@80 { 114 compatible = "fsl,mpc8560-dma-channel", 115 "fsl,eloplus-dma-channel"; 116 reg = <0x80 0x80>; 117 cell-index = <1>; 118 interrupt-parent = <&mpic>; 119 interrupts = <21 2>; 120 }; 121 dma-channel@100 { 122 compatible = "fsl,mpc8560-dma-channel", 123 "fsl,eloplus-dma-channel"; 124 reg = <0x100 0x80>; 125 cell-index = <2>; 126 interrupt-parent = <&mpic>; 127 interrupts = <22 2>; 128 }; 129 dma-channel@180 { 130 compatible = "fsl,mpc8560-dma-channel", 131 "fsl,eloplus-dma-channel"; 132 reg = <0x180 0x80>; 133 cell-index = <3>; 134 interrupt-parent = <&mpic>; 135 interrupts = <23 2>; 136 }; 137 }; 138 139 enet0: ethernet@24000 { 140 #address-cells = <1>; 141 #size-cells = <1>; 142 cell-index = <0>; 143 device_type = "network"; 144 model = "TSEC"; 145 compatible = "gianfar"; 146 reg = <0x24000 0x1000>; 147 ranges = <0x0 0x24000 0x1000>; 148 local-mac-address = [ 00 00 00 00 00 00 ]; 149 interrupts = <29 2 30 2 34 2>; 150 interrupt-parent = <&mpic>; 151 tbi-handle = <&tbi0>; 152 phy-handle = <&phy2>; 153 154 mdio@520 { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "fsl,gianfar-mdio"; 158 reg = <0x520 0x20>; 159 160 phy2: ethernet-phy@2 { 161 interrupt-parent = <&mpic>; 162 interrupts = <5 4>; 163 reg = <2>; 164 }; 165 phy4: ethernet-phy@4 { 166 interrupt-parent = <&mpic>; 167 interrupts = <5 4>; 168 reg = <4>; 169 }; 170 tbi0: tbi-phy@11 { 171 reg = <0x11>; 172 device_type = "tbi-phy"; 173 }; 174 }; 175 }; 176 177 enet1: ethernet@25000 { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 cell-index = <1>; 181 device_type = "network"; 182 model = "TSEC"; 183 compatible = "gianfar"; 184 reg = <0x25000 0x1000>; 185 ranges = <0x0 0x25000 0x1000>; 186 local-mac-address = [ 00 00 00 00 00 00 ]; 187 interrupts = <35 2 36 2 40 2>; 188 interrupt-parent = <&mpic>; 189 tbi-handle = <&tbi1>; 190 phy-handle = <&phy4>; 191 192 mdio@520 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "fsl,gianfar-tbi"; 196 reg = <0x520 0x20>; 197 198 tbi1: tbi-phy@11 { 199 reg = <0x11>; 200 device_type = "tbi-phy"; 201 }; 202 }; 203 }; 204 205 mpic: pic@40000 { 206 interrupt-controller; 207 #address-cells = <0>; 208 #interrupt-cells = <2>; 209 reg = <0x40000 0x40000>; 210 compatible = "chrp,open-pic"; 211 device_type = "open-pic"; 212 }; 213 214 cpm@919c0 { 215 #address-cells = <1>; 216 #size-cells = <1>; 217 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; 218 reg = <0x919c0 0x30>; 219 ranges; 220 221 muram@80000 { 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0 0x80000 0x10000>; 225 226 data@0 { 227 compatible = "fsl,cpm-muram-data"; 228 reg = <0 0x4000 0x9000 0x2000>; 229 }; 230 }; 231 232 brg@919f0 { 233 compatible = "fsl,mpc8560-brg", 234 "fsl,cpm2-brg", 235 "fsl,cpm-brg"; 236 reg = <0x919f0 0x10 0x915f0 0x10>; 237 clock-frequency = <0>; 238 }; 239 240 cpmpic: pic@90c00 { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <2>; 244 interrupts = <46 2>; 245 interrupt-parent = <&mpic>; 246 reg = <0x90c00 0x80>; 247 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 248 }; 249 250 serial0: serial@91a20 { 251 device_type = "serial"; 252 compatible = "fsl,mpc8560-scc-uart", 253 "fsl,cpm2-scc-uart"; 254 reg = <0x91a20 0x20 0x88100 0x100>; 255 fsl,cpm-brg = <2>; 256 fsl,cpm-command = <0x4a00000>; 257 interrupts = <41 8>; 258 interrupt-parent = <&cpmpic>; 259 }; 260 }; 261 }; 262 263 pci0: pci@fdf08000 { 264 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 265 interrupt-map = < 266 267 /* IDSEL 0x0c */ 268 0x6000 0 0 1 &mpic 1 1 269 0x6000 0 0 2 &mpic 2 1 270 0x6000 0 0 3 &mpic 3 1 271 0x6000 0 0 4 &mpic 4 1 272 273 /* IDSEL 0x0d */ 274 0x6800 0 0 1 &mpic 4 1 275 0x6800 0 0 2 &mpic 1 1 276 0x6800 0 0 3 &mpic 2 1 277 0x6800 0 0 4 &mpic 3 1 278 279 /* IDSEL 0x0e */ 280 0x7000 0 0 1 &mpic 3 1 281 0x7000 0 0 2 &mpic 4 1 282 0x7000 0 0 3 &mpic 1 1 283 0x7000 0 0 4 &mpic 2 1 284 285 /* IDSEL 0x0f */ 286 0x7800 0 0 1 &mpic 2 1 287 0x7800 0 0 2 &mpic 3 1 288 0x7800 0 0 3 &mpic 4 1 289 0x7800 0 0 4 &mpic 1 1>; 290 291 interrupt-parent = <&mpic>; 292 interrupts = <24 2>; 293 bus-range = <0 0>; 294 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 295 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 296 clock-frequency = <66666666>; 297 #interrupt-cells = <1>; 298 #size-cells = <2>; 299 #address-cells = <3>; 300 reg = <0xfdf08000 0x1000>; 301 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 302 device_type = "pci"; 303 }; 304}; 305