1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source 4 * 5 * Copyright (C) 2006-2009 Pengutronix 6 * Sascha Hauer <s.hauer@pengutronix.de> 7 * Juergen Beisert <j.beisert@pengutronix.de> 8 * Wolfram Sang <w.sang@pengutronix.de> 9 */ 10 11/include/ "mpc5200b.dtsi" 12 13&gpt0 { fsl,has-wdt; }; 14&gpt2 { gpio-controller; }; 15&gpt3 { gpio-controller; }; 16&gpt4 { gpio-controller; }; 17&gpt5 { gpio-controller; }; 18&gpt6 { gpio-controller; }; 19&gpt7 { gpio-controller; }; 20 21/ { 22 model = "phytec,pcm032"; 23 compatible = "phytec,pcm032"; 24 25 memory { 26 reg = <0x00000000 0x08000000>; // 128MB 27 }; 28 29 soc5200@f0000000 { 30 psc@2000 { /* PSC1 is ac97 */ 31 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 32 cell-index = <0>; 33 }; 34 35 /* PSC2 port is used by CAN1/2 */ 36 psc@2200 { 37 status = "disabled"; 38 }; 39 40 psc@2400 { /* PSC3 in UART mode */ 41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 42 }; 43 44 /* PSC4 is ??? */ 45 psc@2600 { 46 status = "disabled"; 47 }; 48 49 /* PSC5 is ??? */ 50 psc@2800 { 51 status = "disabled"; 52 }; 53 54 psc@2c00 { /* PSC6 in UART mode */ 55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 56 }; 57 58 ethernet@3000 { 59 phy-handle = <&phy0>; 60 }; 61 62 mdio@3000 { 63 phy0: ethernet-phy@0 { 64 reg = <0>; 65 }; 66 }; 67 68 i2c@3d40 { 69 rtc@51 { 70 compatible = "nxp,pcf8563"; 71 reg = <0x51>; 72 }; 73 eeprom@52 { 74 compatible = "catalyst,24c32", "atmel,24c32"; 75 reg = <0x52>; 76 pagesize = <32>; 77 }; 78 }; 79 }; 80 81 pci@f0000d00 { 82 interrupt-map-mask = <0xf800 0 0 7>; 83 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 84 0xc000 0 0 2 &mpc5200_pic 1 1 3 85 0xc000 0 0 3 &mpc5200_pic 1 2 3 86 0xc000 0 0 4 &mpc5200_pic 1 3 3 87 88 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 89 0xc800 0 0 2 &mpc5200_pic 1 2 3 90 0xc800 0 0 3 &mpc5200_pic 1 3 3 91 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 92 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 93 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 94 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 95 }; 96 97 localbus { 98 ranges = <0 0 0xfe000000 0x02000000 99 1 0 0xfc000000 0x02000000 100 2 0 0xfbe00000 0x00200000 101 3 0 0xf9e00000 0x02000000 102 4 0 0xf7e00000 0x02000000 103 5 0 0xe6000000 0x02000000 104 6 0 0xe8000000 0x02000000 105 7 0 0xea000000 0x02000000>; 106 107 flash@0,0 { 108 compatible = "cfi-flash"; 109 reg = <0 0 0x02000000>; 110 bank-width = <4>; 111 #size-cells = <1>; 112 #address-cells = <1>; 113 114 partition@0 { 115 label = "ubootl"; 116 reg = <0x00000000 0x00040000>; 117 }; 118 partition@40000 { 119 label = "kernel"; 120 reg = <0x00040000 0x001c0000>; 121 }; 122 partition@200000 { 123 label = "jffs2"; 124 reg = <0x00200000 0x01d00000>; 125 }; 126 partition@1f00000 { 127 label = "uboot"; 128 reg = <0x01f00000 0x00040000>; 129 }; 130 partition@1f40000 { 131 label = "env"; 132 reg = <0x01f40000 0x00040000>; 133 }; 134 partition@1f80000 { 135 label = "oftree"; 136 reg = <0x01f80000 0x00040000>; 137 }; 138 partition@1fc0000 { 139 label = "space"; 140 reg = <0x01fc0000 0x00040000>; 141 }; 142 }; 143 144 sram@2,0 { 145 compatible = "mtd-ram"; 146 reg = <2 0 0x00200000>; 147 bank-width = <2>; 148 }; 149 150 /* 151 * example snippets for FPGA 152 * 153 * fpga@3,0 { 154 * compatible = "fpga_driver"; 155 * reg = <3 0 0x02000000>; 156 * bank-width = <4>; 157 * }; 158 * 159 * fpga@4,0 { 160 * compatible = "fpga_driver"; 161 * reg = <4 0 0x02000000>; 162 * bank-width = <4>; 163 * }; 164 */ 165 166 /* 167 * example snippets for free chipselects 168 * 169 * device@5,0 { 170 * compatible = "custom_driver"; 171 * reg = <5 0 0x02000000>; 172 * }; 173 * 174 * device@6,0 { 175 * compatible = "custom_driver"; 176 * reg = <6 0 0x02000000>; 177 * }; 178 * 179 * device@7,0 { 180 * compatible = "custom_driver"; 181 * reg = <7 0 0x02000000>; 182 * }; 183 */ 184 }; 185}; 186