1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8378E RDB Device Tree Source 4 * 5 * Copyright 2007, 2008 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9 10/ { 11 compatible = "fsl,mpc8378rdb"; 12 model = "fsl,mpc8378rdb"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci0 = &pci0; 22 pci1 = &pci1; 23 pci2 = &pci2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8378@0 { 31 device_type = "cpu"; 32 reg = <0x0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <32768>; 36 i-cache-size = <32768>; 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 40 }; 41 }; 42 43 memory@0 { 44 device_type = "memory"; 45 reg = <0x00000000 0x10000000>; // 256MB at 0 46 }; 47 48 localbus@e0005000 { 49 #address-cells = <2>; 50 #size-cells = <1>; 51 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 52 reg = <0xe0005000 0x1000>; 53 interrupts = <77 0x8>; 54 interrupt-parent = <&ipic>; 55 56 // CS0 and CS1 are swapped when 57 // booting from nand, but the 58 // addresses are the same. 59 ranges = <0x0 0x0 0xfe000000 0x00800000 60 0x1 0x0 0xe0600000 0x00008000 61 0x2 0x0 0xf0000000 0x00020000 62 0x3 0x0 0xfa000000 0x00008000>; 63 64 flash@0,0 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "cfi-flash"; 68 reg = <0x0 0x0 0x800000>; 69 bank-width = <2>; 70 device-width = <1>; 71 }; 72 73 nand@1,0 { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "fsl,mpc8378-fcm-nand", 77 "fsl,elbc-fcm-nand"; 78 reg = <0x1 0x0 0x8000>; 79 80 u-boot@0 { 81 reg = <0x0 0x100000>; 82 read-only; 83 }; 84 85 kernel@100000 { 86 reg = <0x100000 0x300000>; 87 }; 88 fs@400000 { 89 reg = <0x400000 0x1c00000>; 90 }; 91 }; 92 }; 93 94 immr@e0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 compatible = "simple-bus"; 99 ranges = <0x0 0xe0000000 0x00100000>; 100 reg = <0xe0000000 0x00000200>; 101 bus-frequency = <0>; 102 103 watchdog@200 { 104 device_type = "watchdog"; 105 compatible = "mpc83xx_wdt"; 106 reg = <0x200 0x100>; 107 }; 108 109 gpio1: gpio-controller@c00 { 110 #gpio-cells = <2>; 111 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 112 reg = <0xc00 0x100>; 113 interrupts = <74 0x8>; 114 interrupt-parent = <&ipic>; 115 gpio-controller; 116 }; 117 118 gpio2: gpio-controller@d00 { 119 #gpio-cells = <2>; 120 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio"; 121 reg = <0xd00 0x100>; 122 interrupts = <75 0x8>; 123 interrupt-parent = <&ipic>; 124 gpio-controller; 125 }; 126 127 sleep-nexus { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 compatible = "simple-bus"; 131 sleep = <&pmc 0x0c000000>; 132 ranges; 133 134 i2c@3000 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 cell-index = <0>; 138 compatible = "fsl-i2c"; 139 reg = <0x3000 0x100>; 140 interrupts = <14 0x8>; 141 interrupt-parent = <&ipic>; 142 dfsrr; 143 144 dtt@48 { 145 compatible = "national,lm75"; 146 reg = <0x48>; 147 }; 148 149 at24@50 { 150 compatible = "atmel,24c256"; 151 reg = <0x50>; 152 }; 153 154 rtc@68 { 155 compatible = "dallas,ds1339"; 156 reg = <0x68>; 157 }; 158 159 mcu_pio: mcu@a { 160 #gpio-cells = <2>; 161 compatible = "fsl,mc9s08qg8-mpc8378erdb", 162 "fsl,mcu-mpc8349emitx"; 163 reg = <0x0a>; 164 gpio-controller; 165 }; 166 }; 167 168 sdhci@2e000 { 169 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; 170 reg = <0x2e000 0x1000>; 171 interrupts = <42 0x8>; 172 interrupt-parent = <&ipic>; 173 sdhci,wp-inverted; 174 /* Filled in by U-Boot */ 175 clock-frequency = <111111111>; 176 }; 177 }; 178 179 i2c@3100 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 cell-index = <1>; 183 compatible = "fsl-i2c"; 184 reg = <0x3100 0x100>; 185 interrupts = <15 0x8>; 186 interrupt-parent = <&ipic>; 187 dfsrr; 188 }; 189 190 spi@7000 { 191 cell-index = <0>; 192 compatible = "fsl,spi"; 193 reg = <0x7000 0x1000>; 194 interrupts = <16 0x8>; 195 interrupt-parent = <&ipic>; 196 mode = "cpu"; 197 }; 198 199 dma@82a8 { 200 #address-cells = <1>; 201 #size-cells = <1>; 202 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 203 reg = <0x82a8 4>; 204 ranges = <0 0x8100 0x1a8>; 205 interrupt-parent = <&ipic>; 206 interrupts = <71 8>; 207 cell-index = <0>; 208 dma-channel@0 { 209 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 210 reg = <0 0x80>; 211 cell-index = <0>; 212 interrupt-parent = <&ipic>; 213 interrupts = <71 8>; 214 }; 215 dma-channel@80 { 216 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 217 reg = <0x80 0x80>; 218 cell-index = <1>; 219 interrupt-parent = <&ipic>; 220 interrupts = <71 8>; 221 }; 222 dma-channel@100 { 223 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 224 reg = <0x100 0x80>; 225 cell-index = <2>; 226 interrupt-parent = <&ipic>; 227 interrupts = <71 8>; 228 }; 229 dma-channel@180 { 230 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 231 reg = <0x180 0x28>; 232 cell-index = <3>; 233 interrupt-parent = <&ipic>; 234 interrupts = <71 8>; 235 }; 236 }; 237 238 usb@23000 { 239 compatible = "fsl-usb2-dr"; 240 reg = <0x23000 0x1000>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupt-parent = <&ipic>; 244 interrupts = <38 0x8>; 245 phy_type = "ulpi"; 246 sleep = <&pmc 0x00c00000>; 247 }; 248 249 enet0: ethernet@24000 { 250 #address-cells = <1>; 251 #size-cells = <1>; 252 cell-index = <0>; 253 device_type = "network"; 254 model = "eTSEC"; 255 compatible = "gianfar"; 256 reg = <0x24000 0x1000>; 257 ranges = <0x0 0x24000 0x1000>; 258 local-mac-address = [ 00 00 00 00 00 00 ]; 259 interrupts = <32 0x8 33 0x8 34 0x8>; 260 phy-connection-type = "mii"; 261 interrupt-parent = <&ipic>; 262 tbi-handle = <&tbi0>; 263 phy-handle = <&phy2>; 264 sleep = <&pmc 0xc0000000>; 265 fsl,magic-packet; 266 267 mdio@520 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "fsl,gianfar-mdio"; 271 reg = <0x520 0x20>; 272 273 phy2: ethernet-phy@2 { 274 interrupt-parent = <&ipic>; 275 interrupts = <17 0x8>; 276 reg = <0x2>; 277 }; 278 279 tbi0: tbi-phy@11 { 280 reg = <0x11>; 281 device_type = "tbi-phy"; 282 }; 283 }; 284 }; 285 286 enet1: ethernet@25000 { 287 #address-cells = <1>; 288 #size-cells = <1>; 289 cell-index = <1>; 290 device_type = "network"; 291 model = "eTSEC"; 292 compatible = "gianfar"; 293 reg = <0x25000 0x1000>; 294 ranges = <0x0 0x25000 0x1000>; 295 local-mac-address = [ 00 00 00 00 00 00 ]; 296 interrupts = <35 0x8 36 0x8 37 0x8>; 297 phy-connection-type = "mii"; 298 interrupt-parent = <&ipic>; 299 fixed-link = <1 1 1000 0 0>; 300 tbi-handle = <&tbi1>; 301 sleep = <&pmc 0x30000000>; 302 fsl,magic-packet; 303 304 mdio@520 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "fsl,gianfar-tbi"; 308 reg = <0x520 0x20>; 309 310 tbi1: tbi-phy@11 { 311 reg = <0x11>; 312 device_type = "tbi-phy"; 313 }; 314 }; 315 }; 316 317 serial0: serial@4500 { 318 cell-index = <0>; 319 device_type = "serial"; 320 compatible = "fsl,ns16550", "ns16550"; 321 reg = <0x4500 0x100>; 322 clock-frequency = <0>; 323 interrupts = <9 0x8>; 324 interrupt-parent = <&ipic>; 325 }; 326 327 serial1: serial@4600 { 328 cell-index = <1>; 329 device_type = "serial"; 330 compatible = "fsl,ns16550", "ns16550"; 331 reg = <0x4600 0x100>; 332 clock-frequency = <0>; 333 interrupts = <10 0x8>; 334 interrupt-parent = <&ipic>; 335 }; 336 337 crypto@30000 { 338 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 339 "fsl,sec2.1", "fsl,sec2.0"; 340 reg = <0x30000 0x10000>; 341 interrupts = <11 0x8>; 342 interrupt-parent = <&ipic>; 343 fsl,num-channels = <4>; 344 fsl,channel-fifo-len = <24>; 345 fsl,exec-units-mask = <0x9fe>; 346 fsl,descriptor-types-mask = <0x3ab0ebf>; 347 sleep = <&pmc 0x03000000>; 348 }; 349 350 /* IPIC 351 * interrupts cell = <intr #, sense> 352 * sense values match linux IORESOURCE_IRQ_* defines: 353 * sense == 8: Level, low assertion 354 * sense == 2: Edge, high-to-low change 355 */ 356 ipic: interrupt-controller@700 { 357 compatible = "fsl,ipic"; 358 interrupt-controller; 359 #address-cells = <0>; 360 #interrupt-cells = <2>; 361 reg = <0x700 0x100>; 362 }; 363 364 pmc: power@b00 { 365 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc"; 366 reg = <0xb00 0x100 0xa00 0x100>; 367 interrupts = <80 0x8>; 368 interrupt-parent = <&ipic>; 369 }; 370 }; 371 372 pci0: pci@e0008500 { 373 interrupt-map-mask = <0xf800 0 0 7>; 374 interrupt-map = < 375 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 376 377 /* IDSEL AD14 IRQ6 inta */ 378 0x7000 0x0 0x0 0x1 &ipic 22 0x8 379 380 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 381 0x7800 0x0 0x0 0x1 &ipic 21 0x8 382 0x7800 0x0 0x0 0x2 &ipic 22 0x8 383 0x7800 0x0 0x0 0x4 &ipic 23 0x8 384 385 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 386 0xE000 0x0 0x0 0x1 &ipic 23 0x8 387 0xE000 0x0 0x0 0x2 &ipic 21 0x8 388 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 389 interrupt-parent = <&ipic>; 390 interrupts = <66 0x8>; 391 bus-range = <0 0>; 392 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 393 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 394 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 395 sleep = <&pmc 0x00010000>; 396 clock-frequency = <66666666>; 397 #interrupt-cells = <1>; 398 #size-cells = <2>; 399 #address-cells = <3>; 400 reg = <0xe0008500 0x100 /* internal registers */ 401 0xe0008300 0x8>; /* config space access registers */ 402 compatible = "fsl,mpc8349-pci"; 403 device_type = "pci"; 404 }; 405 406 pci1: pcie@e0009000 { 407 #address-cells = <3>; 408 #size-cells = <2>; 409 #interrupt-cells = <1>; 410 device_type = "pci"; 411 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 412 reg = <0xe0009000 0x00001000>; 413 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 414 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; 415 bus-range = <0 255>; 416 interrupt-map-mask = <0xf800 0 0 7>; 417 interrupt-map = <0 0 0 1 &ipic 1 8 418 0 0 0 2 &ipic 1 8 419 0 0 0 3 &ipic 1 8 420 0 0 0 4 &ipic 1 8>; 421 sleep = <&pmc 0x00300000>; 422 clock-frequency = <0>; 423 424 pcie@0 { 425 #address-cells = <3>; 426 #size-cells = <2>; 427 device_type = "pci"; 428 reg = <0 0 0 0 0>; 429 ranges = <0x02000000 0 0xa8000000 430 0x02000000 0 0xa8000000 431 0 0x10000000 432 0x01000000 0 0x00000000 433 0x01000000 0 0x00000000 434 0 0x00800000>; 435 }; 436 }; 437 438 pci2: pcie@e000a000 { 439 #address-cells = <3>; 440 #size-cells = <2>; 441 #interrupt-cells = <1>; 442 device_type = "pci"; 443 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 444 reg = <0xe000a000 0x00001000>; 445 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 446 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; 447 bus-range = <0 255>; 448 interrupt-map-mask = <0xf800 0 0 7>; 449 interrupt-map = <0 0 0 1 &ipic 2 8 450 0 0 0 2 &ipic 2 8 451 0 0 0 3 &ipic 2 8 452 0 0 0 4 &ipic 2 8>; 453 sleep = <&pmc 0x000c0000>; 454 clock-frequency = <0>; 455 456 pcie@0 { 457 #address-cells = <3>; 458 #size-cells = <2>; 459 device_type = "pci"; 460 reg = <0 0 0 0 0>; 461 ranges = <0x02000000 0 0xc8000000 462 0x02000000 0 0xc8000000 463 0 0x10000000 464 0x01000000 0 0x00000000 465 0x01000000 0 0x00000000 466 0 0x00800000>; 467 }; 468 }; 469 470 leds { 471 compatible = "gpio-leds"; 472 473 pwr { 474 gpios = <&mcu_pio 0 0>; 475 default-state = "on"; 476 }; 477 478 hdd { 479 gpios = <&mcu_pio 1 0>; 480 linux,default-trigger = "disk-activity"; 481 }; 482 }; 483}; 484