1/* 2 * MPC8360E RDK Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * Copyright 2007-2008 MontaVista Software, Inc. 6 * 7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15/dts-v1/; 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 compatible = "fsl,mpc8360rdk"; 21 22 aliases { 23 serial0 = &serial0; 24 serial1 = &serial1; 25 serial2 = &serial2; 26 serial3 = &serial3; 27 ethernet0 = &enet0; 28 ethernet1 = &enet1; 29 ethernet2 = &enet2; 30 ethernet3 = &enet3; 31 pci0 = &pci0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 PowerPC,8360@0 { 39 device_type = "cpu"; 40 reg = <0>; 41 d-cache-line-size = <32>; 42 i-cache-line-size = <32>; 43 d-cache-size = <32768>; 44 i-cache-size = <32768>; 45 /* filled by u-boot */ 46 timebase-frequency = <0>; 47 bus-frequency = <0>; 48 clock-frequency = <0>; 49 }; 50 }; 51 52 memory { 53 device_type = "memory"; 54 /* filled by u-boot */ 55 reg = <0 0>; 56 }; 57 58 soc@e0000000 { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 device_type = "soc"; 62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", 63 "simple-bus"; 64 ranges = <0 0xe0000000 0x200000>; 65 reg = <0xe0000000 0x200>; 66 /* filled by u-boot */ 67 bus-frequency = <0>; 68 69 wdt@200 { 70 compatible = "mpc83xx_wdt"; 71 reg = <0x200 0x100>; 72 }; 73 74 pmc: power@b00 { 75 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; 76 reg = <0xb00 0x100 0xa00 0x100>; 77 interrupts = <80 0x8>; 78 interrupt-parent = <&ipic>; 79 }; 80 81 i2c@3000 { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 cell-index = <0>; 85 compatible = "fsl-i2c"; 86 reg = <0x3000 0x100>; 87 interrupts = <14 8>; 88 interrupt-parent = <&ipic>; 89 dfsrr; 90 }; 91 92 i2c@3100 { 93 #address-cells = <1>; 94 #size-cells = <0>; 95 cell-index = <1>; 96 compatible = "fsl-i2c"; 97 reg = <0x3100 0x100>; 98 interrupts = <16 8>; 99 interrupt-parent = <&ipic>; 100 dfsrr; 101 }; 102 103 serial0: serial@4500 { 104 device_type = "serial"; 105 compatible = "fsl,ns16550", "ns16550"; 106 reg = <0x4500 0x100>; 107 interrupts = <9 8>; 108 interrupt-parent = <&ipic>; 109 /* filled by u-boot */ 110 clock-frequency = <0>; 111 }; 112 113 serial1: serial@4600 { 114 device_type = "serial"; 115 compatible = "fsl,ns16550", "ns16550"; 116 reg = <0x4600 0x100>; 117 interrupts = <10 8>; 118 interrupt-parent = <&ipic>; 119 /* filled by u-boot */ 120 clock-frequency = <0>; 121 }; 122 123 dma@82a8 { 124 #address-cells = <1>; 125 #size-cells = <1>; 126 compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 127 reg = <0x82a8 4>; 128 ranges = <0 0x8100 0x1a8>; 129 interrupt-parent = <&ipic>; 130 interrupts = <71 8>; 131 cell-index = <0>; 132 dma-channel@0 { 133 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 134 reg = <0 0x80>; 135 cell-index = <0>; 136 interrupt-parent = <&ipic>; 137 interrupts = <71 8>; 138 }; 139 dma-channel@80 { 140 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 141 reg = <0x80 0x80>; 142 cell-index = <1>; 143 interrupt-parent = <&ipic>; 144 interrupts = <71 8>; 145 }; 146 dma-channel@100 { 147 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 148 reg = <0x100 0x80>; 149 cell-index = <2>; 150 interrupt-parent = <&ipic>; 151 interrupts = <71 8>; 152 }; 153 dma-channel@180 { 154 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 155 reg = <0x180 0x28>; 156 cell-index = <3>; 157 interrupt-parent = <&ipic>; 158 interrupts = <71 8>; 159 }; 160 }; 161 162 crypto@30000 { 163 compatible = "fsl,sec2.0"; 164 reg = <0x30000 0x10000>; 165 interrupts = <11 0x8>; 166 interrupt-parent = <&ipic>; 167 fsl,num-channels = <4>; 168 fsl,channel-fifo-len = <24>; 169 fsl,exec-units-mask = <0x7e>; 170 fsl,descriptor-types-mask = <0x01010ebf>; 171 sleep = <&pmc 0x03000000>; 172 }; 173 174 ipic: interrupt-controller@700 { 175 #address-cells = <0>; 176 #interrupt-cells = <2>; 177 compatible = "fsl,pq2pro-pic", "fsl,ipic"; 178 interrupt-controller; 179 reg = <0x700 0x100>; 180 }; 181 182 qe_pio_b: gpio-controller@1418 { 183 #gpio-cells = <2>; 184 compatible = "fsl,mpc8360-qe-pario-bank", 185 "fsl,mpc8323-qe-pario-bank"; 186 reg = <0x1418 0x18>; 187 gpio-controller; 188 }; 189 190 qe_pio_e: gpio-controller@1460 { 191 #gpio-cells = <2>; 192 compatible = "fsl,mpc8360-qe-pario-bank", 193 "fsl,mpc8323-qe-pario-bank"; 194 reg = <0x1460 0x18>; 195 gpio-controller; 196 }; 197 198 qe@100000 { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 device_type = "qe"; 202 compatible = "fsl,qe", "simple-bus"; 203 ranges = <0 0x100000 0x100000>; 204 reg = <0x100000 0x480>; 205 /* filled by u-boot */ 206 clock-frequency = <0>; 207 bus-frequency = <0>; 208 brg-frequency = <0>; 209 fsl,qe-num-riscs = <2>; 210 fsl,qe-num-snums = <28>; 211 212 muram@10000 { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 216 ranges = <0 0x10000 0xc000>; 217 218 data-only@0 { 219 compatible = "fsl,qe-muram-data", 220 "fsl,cpm-muram-data"; 221 reg = <0 0xc000>; 222 }; 223 }; 224 225 timer@440 { 226 compatible = "fsl,mpc8360-qe-gtm", 227 "fsl,qe-gtm", "fsl,gtm"; 228 reg = <0x440 0x40>; 229 interrupts = <12 13 14 15>; 230 interrupt-parent = <&qeic>; 231 clock-frequency = <166666666>; 232 }; 233 234 usb@6c0 { 235 compatible = "fsl,mpc8360-qe-usb", 236 "fsl,mpc8323-qe-usb"; 237 reg = <0x6c0 0x40 0x8b00 0x100>; 238 interrupts = <11>; 239 interrupt-parent = <&qeic>; 240 fsl,fullspeed-clock = "clk21"; 241 gpios = <&qe_pio_b 2 0 /* USBOE */ 242 &qe_pio_b 3 0 /* USBTP */ 243 &qe_pio_b 8 0 /* USBTN */ 244 &qe_pio_b 9 0 /* USBRP */ 245 &qe_pio_b 11 0 /* USBRN */ 246 &qe_pio_e 20 0 /* SPEED */ 247 &qe_pio_e 21 1 /* POWER */>; 248 }; 249 250 spi@4c0 { 251 cell-index = <0>; 252 compatible = "fsl,spi"; 253 reg = <0x4c0 0x40>; 254 interrupts = <2>; 255 interrupt-parent = <&qeic>; 256 mode = "cpu-qe"; 257 }; 258 259 spi@500 { 260 cell-index = <1>; 261 compatible = "fsl,spi"; 262 reg = <0x500 0x40>; 263 interrupts = <1>; 264 interrupt-parent = <&qeic>; 265 mode = "cpu-qe"; 266 }; 267 268 enet0: ucc@2000 { 269 device_type = "network"; 270 compatible = "ucc_geth"; 271 cell-index = <1>; 272 reg = <0x2000 0x200>; 273 interrupts = <32>; 274 interrupt-parent = <&qeic>; 275 rx-clock-name = "none"; 276 tx-clock-name = "clk9"; 277 phy-handle = <&phy2>; 278 phy-connection-type = "rgmii-rxid"; 279 /* filled by u-boot */ 280 local-mac-address = [ 00 00 00 00 00 00 ]; 281 }; 282 283 enet1: ucc@3000 { 284 device_type = "network"; 285 compatible = "ucc_geth"; 286 cell-index = <2>; 287 reg = <0x3000 0x200>; 288 interrupts = <33>; 289 interrupt-parent = <&qeic>; 290 rx-clock-name = "none"; 291 tx-clock-name = "clk4"; 292 phy-handle = <&phy4>; 293 phy-connection-type = "rgmii-rxid"; 294 /* filled by u-boot */ 295 local-mac-address = [ 00 00 00 00 00 00 ]; 296 }; 297 298 enet2: ucc@2600 { 299 device_type = "network"; 300 compatible = "ucc_geth"; 301 cell-index = <7>; 302 reg = <0x2600 0x200>; 303 interrupts = <42>; 304 interrupt-parent = <&qeic>; 305 rx-clock-name = "clk20"; 306 tx-clock-name = "clk19"; 307 phy-handle = <&phy1>; 308 phy-connection-type = "mii"; 309 /* filled by u-boot */ 310 local-mac-address = [ 00 00 00 00 00 00 ]; 311 }; 312 313 enet3: ucc@3200 { 314 device_type = "network"; 315 compatible = "ucc_geth"; 316 cell-index = <4>; 317 reg = <0x3200 0x200>; 318 interrupts = <35>; 319 interrupt-parent = <&qeic>; 320 rx-clock-name = "clk8"; 321 tx-clock-name = "clk7"; 322 phy-handle = <&phy3>; 323 phy-connection-type = "mii"; 324 /* filled by u-boot */ 325 local-mac-address = [ 00 00 00 00 00 00 ]; 326 }; 327 328 mdio@2120 { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 compatible = "fsl,ucc-mdio"; 332 reg = <0x2120 0x18>; 333 334 phy1: ethernet-phy@1 { 335 compatible = "national,DP83848VV"; 336 reg = <1>; 337 }; 338 339 phy2: ethernet-phy@2 { 340 compatible = "broadcom,BCM5481UA2KMLG"; 341 reg = <2>; 342 }; 343 344 phy3: ethernet-phy@3 { 345 compatible = "national,DP83848VV"; 346 reg = <3>; 347 }; 348 349 phy4: ethernet-phy@4 { 350 compatible = "broadcom,BCM5481UA2KMLG"; 351 reg = <4>; 352 }; 353 }; 354 355 serial2: ucc@2400 { 356 device_type = "serial"; 357 compatible = "ucc_uart"; 358 reg = <0x2400 0x200>; 359 cell-index = <5>; 360 port-number = <0>; 361 rx-clock-name = "brg7"; 362 tx-clock-name = "brg8"; 363 interrupts = <40>; 364 interrupt-parent = <&qeic>; 365 soft-uart; 366 }; 367 368 serial3: ucc@3400 { 369 device_type = "serial"; 370 compatible = "ucc_uart"; 371 reg = <0x3400 0x200>; 372 cell-index = <6>; 373 port-number = <1>; 374 rx-clock-name = "brg13"; 375 tx-clock-name = "brg14"; 376 interrupts = <41>; 377 interrupt-parent = <&qeic>; 378 soft-uart; 379 }; 380 381 qeic: interrupt-controller@80 { 382 #address-cells = <0>; 383 #interrupt-cells = <1>; 384 compatible = "fsl,qe-ic"; 385 interrupt-controller; 386 reg = <0x80 0x80>; 387 big-endian; 388 interrupts = <32 8 33 8>; 389 interrupt-parent = <&ipic>; 390 }; 391 }; 392 }; 393 394 localbus@e0005000 { 395 #address-cells = <2>; 396 #size-cells = <1>; 397 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 398 "simple-bus"; 399 reg = <0xe0005000 0xd8>; 400 ranges = <0 0 0xff800000 0x0800000 401 1 0 0x60000000 0x0001000 402 2 0 0x70000000 0x4000000>; 403 404 flash@0,0 { 405 compatible = "intel,PC28F640P30T85", "cfi-flash"; 406 reg = <0 0 0x800000>; 407 bank-width = <2>; 408 device-width = <1>; 409 }; 410 411 upm@1,0 { 412 compatible = "fsl,upm-nand"; 413 reg = <1 0 1>; 414 fsl,upm-addr-offset = <16>; 415 fsl,upm-cmd-offset = <8>; 416 gpios = <&qe_pio_e 18 0>; 417 418 flash { 419 compatible = "stm,nand512-a"; 420 }; 421 }; 422 423 display@2,0 { 424 device_type = "display"; 425 compatible = "fujitsu,MB86277", "fujitsu,mint"; 426 reg = <2 0 0x4000000>; 427 fujitsu,sh3; 428 little-endian; 429 /* filled by u-boot */ 430 address = <0>; 431 depth = <0>; 432 width = <0>; 433 height = <0>; 434 linebytes = <0>; 435 /* linux,opened; - added by uboot */ 436 }; 437 }; 438 439 pci0: pci@e0008500 { 440 #address-cells = <3>; 441 #size-cells = <2>; 442 #interrupt-cells = <1>; 443 device_type = "pci"; 444 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; 445 reg = <0xe0008500 0x100 /* internal registers */ 446 0xe0008300 0x8>; /* config space access registers */ 447 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 448 0x42000000 0 0x80000000 0x80000000 0 0x10000000 449 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; 450 interrupts = <66 8>; 451 interrupt-parent = <&ipic>; 452 interrupt-map-mask = <0xf800 0 0 7>; 453 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ 454 0xa000 0 0 1 &ipic 18 8 455 0xa000 0 0 2 &ipic 19 8 456 457 /* PCI1 IDSEL 0x15 AD21 */ 458 0xa800 0 0 1 &ipic 19 8 459 0xa800 0 0 2 &ipic 20 8 460 0xa800 0 0 3 &ipic 21 8 461 0xa800 0 0 4 &ipic 18 8>; 462 sleep = <&pmc 0x00010000>; 463 /* filled by u-boot */ 464 bus-range = <0 0>; 465 clock-frequency = <0>; 466 }; 467}; 468