1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8360E RDK Device Tree Source 4 * 5 * Copyright 2006 Freescale Semiconductor Inc. 6 * Copyright 2007-2008 MontaVista Software, Inc. 7 * 8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 compatible = "fsl,mpc8360rdk"; 17 model = "fsl,mpc8360rdk"; 18 19 aliases { 20 serial0 = &serial0; 21 serial1 = &serial1; 22 serial2 = &serial2; 23 serial3 = &serial3; 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 pci0 = &pci0; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8360@0 { 36 device_type = "cpu"; 37 reg = <0>; 38 d-cache-line-size = <32>; 39 i-cache-line-size = <32>; 40 d-cache-size = <32768>; 41 i-cache-size = <32768>; 42 /* filled by u-boot */ 43 timebase-frequency = <0>; 44 bus-frequency = <0>; 45 clock-frequency = <0>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 /* filled by u-boot */ 52 reg = <0 0>; 53 }; 54 55 soc@e0000000 { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 device_type = "soc"; 59 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", 60 "simple-bus"; 61 ranges = <0 0xe0000000 0x200000>; 62 reg = <0xe0000000 0x200>; 63 /* filled by u-boot */ 64 bus-frequency = <0>; 65 66 watchdog@200 { 67 compatible = "mpc83xx_wdt"; 68 reg = <0x200 0x100>; 69 }; 70 71 pmc: power@b00 { 72 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; 73 reg = <0xb00 0x100 0xa00 0x100>; 74 interrupts = <80 0x8>; 75 interrupt-parent = <&ipic>; 76 }; 77 78 i2c@3000 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 cell-index = <0>; 82 compatible = "fsl-i2c"; 83 reg = <0x3000 0x100>; 84 interrupts = <14 8>; 85 interrupt-parent = <&ipic>; 86 dfsrr; 87 }; 88 89 i2c@3100 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 cell-index = <1>; 93 compatible = "fsl-i2c"; 94 reg = <0x3100 0x100>; 95 interrupts = <16 8>; 96 interrupt-parent = <&ipic>; 97 dfsrr; 98 }; 99 100 serial0: serial@4500 { 101 device_type = "serial"; 102 compatible = "fsl,ns16550", "ns16550"; 103 reg = <0x4500 0x100>; 104 interrupts = <9 8>; 105 interrupt-parent = <&ipic>; 106 /* filled by u-boot */ 107 clock-frequency = <0>; 108 }; 109 110 serial1: serial@4600 { 111 device_type = "serial"; 112 compatible = "fsl,ns16550", "ns16550"; 113 reg = <0x4600 0x100>; 114 interrupts = <10 8>; 115 interrupt-parent = <&ipic>; 116 /* filled by u-boot */ 117 clock-frequency = <0>; 118 }; 119 120 dma@82a8 { 121 #address-cells = <1>; 122 #size-cells = <1>; 123 compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; 124 reg = <0x82a8 4>; 125 ranges = <0 0x8100 0x1a8>; 126 interrupt-parent = <&ipic>; 127 interrupts = <71 8>; 128 cell-index = <0>; 129 dma-channel@0 { 130 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 131 reg = <0 0x80>; 132 cell-index = <0>; 133 interrupt-parent = <&ipic>; 134 interrupts = <71 8>; 135 }; 136 dma-channel@80 { 137 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 138 reg = <0x80 0x80>; 139 cell-index = <1>; 140 interrupt-parent = <&ipic>; 141 interrupts = <71 8>; 142 }; 143 dma-channel@100 { 144 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 145 reg = <0x100 0x80>; 146 cell-index = <2>; 147 interrupt-parent = <&ipic>; 148 interrupts = <71 8>; 149 }; 150 dma-channel@180 { 151 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; 152 reg = <0x180 0x28>; 153 cell-index = <3>; 154 interrupt-parent = <&ipic>; 155 interrupts = <71 8>; 156 }; 157 }; 158 159 crypto@30000 { 160 compatible = "fsl,sec2.0"; 161 reg = <0x30000 0x10000>; 162 interrupts = <11 0x8>; 163 interrupt-parent = <&ipic>; 164 fsl,num-channels = <4>; 165 fsl,channel-fifo-len = <24>; 166 fsl,exec-units-mask = <0x7e>; 167 fsl,descriptor-types-mask = <0x01010ebf>; 168 sleep = <&pmc 0x03000000>; 169 }; 170 171 ipic: interrupt-controller@700 { 172 #address-cells = <0>; 173 #interrupt-cells = <2>; 174 compatible = "fsl,pq2pro-pic", "fsl,ipic"; 175 interrupt-controller; 176 reg = <0x700 0x100>; 177 }; 178 179 qe_pio_b: gpio-controller@1418 { 180 #gpio-cells = <2>; 181 compatible = "fsl,mpc8360-qe-pario-bank", 182 "fsl,mpc8323-qe-pario-bank"; 183 reg = <0x1418 0x18>; 184 gpio-controller; 185 }; 186 187 qe_pio_e: gpio-controller@1460 { 188 #gpio-cells = <2>; 189 compatible = "fsl,mpc8360-qe-pario-bank", 190 "fsl,mpc8323-qe-pario-bank"; 191 reg = <0x1460 0x18>; 192 gpio-controller; 193 }; 194 195 qe@100000 { 196 #address-cells = <1>; 197 #size-cells = <1>; 198 device_type = "qe"; 199 compatible = "fsl,qe", "simple-bus"; 200 ranges = <0 0x100000 0x100000>; 201 reg = <0x100000 0x480>; 202 /* filled by u-boot */ 203 clock-frequency = <0>; 204 bus-frequency = <0>; 205 brg-frequency = <0>; 206 fsl,qe-num-riscs = <2>; 207 fsl,qe-num-snums = <28>; 208 209 muram@10000 { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 213 ranges = <0 0x10000 0xc000>; 214 215 data-only@0 { 216 compatible = "fsl,qe-muram-data", 217 "fsl,cpm-muram-data"; 218 reg = <0 0xc000>; 219 }; 220 }; 221 222 timer@440 { 223 compatible = "fsl,mpc8360-qe-gtm", 224 "fsl,qe-gtm", "fsl,gtm"; 225 reg = <0x440 0x40>; 226 interrupts = <12 13 14 15>; 227 interrupt-parent = <&qeic>; 228 clock-frequency = <166666666>; 229 }; 230 231 usb@6c0 { 232 compatible = "fsl,mpc8360-qe-usb", 233 "fsl,mpc8323-qe-usb"; 234 reg = <0x6c0 0x40 0x8b00 0x100>; 235 interrupts = <11>; 236 interrupt-parent = <&qeic>; 237 fsl,fullspeed-clock = "clk21"; 238 gpios = <&qe_pio_b 2 0 /* USBOE */ 239 &qe_pio_b 3 0 /* USBTP */ 240 &qe_pio_b 8 0 /* USBTN */ 241 &qe_pio_b 9 0 /* USBRP */ 242 &qe_pio_b 11 0 /* USBRN */ 243 &qe_pio_e 20 0 /* SPEED */ 244 &qe_pio_e 21 1 /* POWER */>; 245 }; 246 247 spi@4c0 { 248 cell-index = <0>; 249 compatible = "fsl,spi"; 250 reg = <0x4c0 0x40>; 251 interrupts = <2>; 252 interrupt-parent = <&qeic>; 253 mode = "cpu-qe"; 254 }; 255 256 spi@500 { 257 cell-index = <1>; 258 compatible = "fsl,spi"; 259 reg = <0x500 0x40>; 260 interrupts = <1>; 261 interrupt-parent = <&qeic>; 262 mode = "cpu-qe"; 263 }; 264 265 enet0: ucc@2000 { 266 device_type = "network"; 267 compatible = "ucc_geth"; 268 cell-index = <1>; 269 reg = <0x2000 0x200>; 270 interrupts = <32>; 271 interrupt-parent = <&qeic>; 272 rx-clock-name = "none"; 273 tx-clock-name = "clk9"; 274 phy-handle = <&phy2>; 275 phy-connection-type = "rgmii-rxid"; 276 /* filled by u-boot */ 277 local-mac-address = [ 00 00 00 00 00 00 ]; 278 }; 279 280 enet1: ucc@3000 { 281 device_type = "network"; 282 compatible = "ucc_geth"; 283 cell-index = <2>; 284 reg = <0x3000 0x200>; 285 interrupts = <33>; 286 interrupt-parent = <&qeic>; 287 rx-clock-name = "none"; 288 tx-clock-name = "clk4"; 289 phy-handle = <&phy4>; 290 phy-connection-type = "rgmii-rxid"; 291 /* filled by u-boot */ 292 local-mac-address = [ 00 00 00 00 00 00 ]; 293 }; 294 295 enet2: ucc@2600 { 296 device_type = "network"; 297 compatible = "ucc_geth"; 298 cell-index = <7>; 299 reg = <0x2600 0x200>; 300 interrupts = <42>; 301 interrupt-parent = <&qeic>; 302 rx-clock-name = "clk20"; 303 tx-clock-name = "clk19"; 304 phy-handle = <&phy1>; 305 phy-connection-type = "mii"; 306 /* filled by u-boot */ 307 local-mac-address = [ 00 00 00 00 00 00 ]; 308 }; 309 310 enet3: ucc@3200 { 311 device_type = "network"; 312 compatible = "ucc_geth"; 313 cell-index = <4>; 314 reg = <0x3200 0x200>; 315 interrupts = <35>; 316 interrupt-parent = <&qeic>; 317 rx-clock-name = "clk8"; 318 tx-clock-name = "clk7"; 319 phy-handle = <&phy3>; 320 phy-connection-type = "mii"; 321 /* filled by u-boot */ 322 local-mac-address = [ 00 00 00 00 00 00 ]; 323 }; 324 325 mdio@2120 { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 compatible = "fsl,ucc-mdio"; 329 reg = <0x2120 0x18>; 330 331 phy1: ethernet-phy@1 { 332 compatible = "national,DP83848VV"; 333 reg = <1>; 334 }; 335 336 phy2: ethernet-phy@2 { 337 compatible = "broadcom,BCM5481UA2KMLG"; 338 reg = <2>; 339 }; 340 341 phy3: ethernet-phy@3 { 342 compatible = "national,DP83848VV"; 343 reg = <3>; 344 }; 345 346 phy4: ethernet-phy@4 { 347 compatible = "broadcom,BCM5481UA2KMLG"; 348 reg = <4>; 349 }; 350 }; 351 352 serial2: ucc@2400 { 353 device_type = "serial"; 354 compatible = "ucc_uart"; 355 reg = <0x2400 0x200>; 356 cell-index = <5>; 357 port-number = <0>; 358 rx-clock-name = "brg7"; 359 tx-clock-name = "brg8"; 360 interrupts = <40>; 361 interrupt-parent = <&qeic>; 362 soft-uart; 363 }; 364 365 serial3: ucc@3400 { 366 device_type = "serial"; 367 compatible = "ucc_uart"; 368 reg = <0x3400 0x200>; 369 cell-index = <6>; 370 port-number = <1>; 371 rx-clock-name = "brg13"; 372 tx-clock-name = "brg14"; 373 interrupts = <41>; 374 interrupt-parent = <&qeic>; 375 soft-uart; 376 }; 377 378 qeic: interrupt-controller@80 { 379 #address-cells = <0>; 380 #interrupt-cells = <1>; 381 compatible = "fsl,qe-ic"; 382 interrupt-controller; 383 reg = <0x80 0x80>; 384 big-endian; 385 interrupts = <32 8 33 8>; 386 interrupt-parent = <&ipic>; 387 }; 388 }; 389 }; 390 391 localbus@e0005000 { 392 #address-cells = <2>; 393 #size-cells = <1>; 394 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", 395 "simple-bus"; 396 reg = <0xe0005000 0xd8>; 397 ranges = <0 0 0xff800000 0x0800000 398 1 0 0x60000000 0x0001000 399 2 0 0x70000000 0x4000000>; 400 401 flash@0,0 { 402 compatible = "intel,PC28F640P30T85", "cfi-flash"; 403 reg = <0 0 0x800000>; 404 bank-width = <2>; 405 device-width = <1>; 406 }; 407 408 upm@1,0 { 409 compatible = "fsl,upm-nand"; 410 reg = <1 0 1>; 411 fsl,upm-addr-offset = <16>; 412 fsl,upm-cmd-offset = <8>; 413 gpios = <&qe_pio_e 18 0>; 414 415 flash { 416 compatible = "st,nand512-a"; 417 }; 418 }; 419 420 display@2,0 { 421 device_type = "display"; 422 compatible = "fujitsu,MB86277", "fujitsu,mint"; 423 reg = <2 0 0x4000000>; 424 fujitsu,sh3; 425 little-endian; 426 /* filled by u-boot */ 427 address = <0>; 428 depth = <0>; 429 width = <0>; 430 height = <0>; 431 linebytes = <0>; 432 /* linux,opened; - added by uboot */ 433 }; 434 }; 435 436 pci0: pci@e0008500 { 437 #address-cells = <3>; 438 #size-cells = <2>; 439 #interrupt-cells = <1>; 440 device_type = "pci"; 441 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; 442 reg = <0xe0008500 0x100 /* internal registers */ 443 0xe0008300 0x8>; /* config space access registers */ 444 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 445 0x42000000 0 0x80000000 0x80000000 0 0x10000000 446 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; 447 interrupts = <66 8>; 448 interrupt-parent = <&ipic>; 449 interrupt-map-mask = <0xf800 0 0 7>; 450 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ 451 0xa000 0 0 1 &ipic 18 8 452 0xa000 0 0 2 &ipic 19 8 453 454 /* PCI1 IDSEL 0x15 AD21 */ 455 0xa800 0 0 1 &ipic 19 8 456 0xa800 0 0 2 &ipic 20 8 457 0xa800 0 0 3 &ipic 21 8 458 0xa800 0 0 4 &ipic 18 8>; 459 sleep = <&pmc 0x00010000>; 460 /* filled by u-boot */ 461 bus-range = <0 0>; 462 clock-frequency = <0>; 463 }; 464}; 465