1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8315E RDB Device Tree Source 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9 10/ { 11 compatible = "fsl,mpc8315erdb"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 aliases { 16 ethernet0 = &enet0; 17 ethernet1 = &enet1; 18 serial0 = &serial0; 19 serial1 = &serial1; 20 pci0 = &pci0; 21 pci1 = &pci1; 22 pci2 = &pci2; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8315@0 { 30 device_type = "cpu"; 31 reg = <0x0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <16384>; 35 i-cache-size = <16384>; 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 39 }; 40 }; 41 42 memory { 43 device_type = "memory"; 44 reg = <0x00000000 0x08000000>; // 128MB at 0 45 }; 46 47 localbus@e0005000 { 48 #address-cells = <2>; 49 #size-cells = <1>; 50 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 51 reg = <0xe0005000 0x1000>; 52 interrupts = <77 0x8>; 53 interrupt-parent = <&ipic>; 54 55 // CS0 and CS1 are swapped when 56 // booting from nand, but the 57 // addresses are the same. 58 ranges = <0x0 0x0 0xfe000000 0x00800000 59 0x1 0x0 0xe0600000 0x00002000 60 0x2 0x0 0xf0000000 0x00020000 61 0x3 0x0 0xfa000000 0x00008000>; 62 63 flash@0,0 { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "cfi-flash"; 67 reg = <0x0 0x0 0x800000>; 68 bank-width = <2>; 69 device-width = <1>; 70 }; 71 72 nand@1,0 { 73 #address-cells = <1>; 74 #size-cells = <1>; 75 compatible = "fsl,mpc8315-fcm-nand", 76 "fsl,elbc-fcm-nand"; 77 reg = <0x1 0x0 0x2000>; 78 79 u-boot@0 { 80 reg = <0x0 0x100000>; 81 read-only; 82 }; 83 84 kernel@100000 { 85 reg = <0x100000 0x300000>; 86 }; 87 fs@400000 { 88 reg = <0x400000 0x1c00000>; 89 }; 90 }; 91 }; 92 93 immr@e0000000 { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 device_type = "soc"; 97 compatible = "fsl,mpc8315-immr", "simple-bus"; 98 ranges = <0 0xe0000000 0x00100000>; 99 reg = <0xe0000000 0x00000200>; 100 bus-frequency = <0>; 101 102 wdt@200 { 103 device_type = "watchdog"; 104 compatible = "mpc83xx_wdt"; 105 reg = <0x200 0x100>; 106 }; 107 108 i2c@3000 { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 cell-index = <0>; 112 compatible = "fsl-i2c"; 113 reg = <0x3000 0x100>; 114 interrupts = <14 0x8>; 115 interrupt-parent = <&ipic>; 116 dfsrr; 117 rtc@68 { 118 compatible = "dallas,ds1339"; 119 reg = <0x68>; 120 }; 121 122 mcu_pio: mcu@a { 123 #gpio-cells = <2>; 124 compatible = "fsl,mc9s08qg8-mpc8315erdb", 125 "fsl,mcu-mpc8349emitx"; 126 reg = <0x0a>; 127 gpio-controller; 128 }; 129 }; 130 131 spi@7000 { 132 cell-index = <0>; 133 compatible = "fsl,spi"; 134 reg = <0x7000 0x1000>; 135 interrupts = <16 0x8>; 136 interrupt-parent = <&ipic>; 137 mode = "cpu"; 138 }; 139 140 dma@82a8 { 141 #address-cells = <1>; 142 #size-cells = <1>; 143 compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; 144 reg = <0x82a8 4>; 145 ranges = <0 0x8100 0x1a8>; 146 interrupt-parent = <&ipic>; 147 interrupts = <71 8>; 148 cell-index = <0>; 149 dma-channel@0 { 150 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 151 reg = <0 0x80>; 152 cell-index = <0>; 153 interrupt-parent = <&ipic>; 154 interrupts = <71 8>; 155 }; 156 dma-channel@80 { 157 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 158 reg = <0x80 0x80>; 159 cell-index = <1>; 160 interrupt-parent = <&ipic>; 161 interrupts = <71 8>; 162 }; 163 dma-channel@100 { 164 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 165 reg = <0x100 0x80>; 166 cell-index = <2>; 167 interrupt-parent = <&ipic>; 168 interrupts = <71 8>; 169 }; 170 dma-channel@180 { 171 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 172 reg = <0x180 0x28>; 173 cell-index = <3>; 174 interrupt-parent = <&ipic>; 175 interrupts = <71 8>; 176 }; 177 }; 178 179 usb@23000 { 180 compatible = "fsl-usb2-dr"; 181 reg = <0x23000 0x1000>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 interrupt-parent = <&ipic>; 185 interrupts = <38 0x8>; 186 phy_type = "utmi"; 187 }; 188 189 enet0: ethernet@24000 { 190 #address-cells = <1>; 191 #size-cells = <1>; 192 cell-index = <0>; 193 device_type = "network"; 194 model = "eTSEC"; 195 compatible = "gianfar"; 196 reg = <0x24000 0x1000>; 197 ranges = <0x0 0x24000 0x1000>; 198 local-mac-address = [ 00 00 00 00 00 00 ]; 199 interrupts = <32 0x8 33 0x8 34 0x8>; 200 interrupt-parent = <&ipic>; 201 tbi-handle = <&tbi0>; 202 phy-handle = < &phy0 >; 203 fsl,magic-packet; 204 205 mdio@520 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "fsl,gianfar-mdio"; 209 reg = <0x520 0x20>; 210 211 phy0: ethernet-phy@0 { 212 interrupt-parent = <&ipic>; 213 interrupts = <20 0x8>; 214 reg = <0x0>; 215 }; 216 217 phy1: ethernet-phy@1 { 218 interrupt-parent = <&ipic>; 219 interrupts = <19 0x8>; 220 reg = <0x1>; 221 }; 222 223 tbi0: tbi-phy@11 { 224 reg = <0x11>; 225 device_type = "tbi-phy"; 226 }; 227 }; 228 }; 229 230 enet1: ethernet@25000 { 231 #address-cells = <1>; 232 #size-cells = <1>; 233 cell-index = <1>; 234 device_type = "network"; 235 model = "eTSEC"; 236 compatible = "gianfar"; 237 reg = <0x25000 0x1000>; 238 ranges = <0x0 0x25000 0x1000>; 239 local-mac-address = [ 00 00 00 00 00 00 ]; 240 interrupts = <35 0x8 36 0x8 37 0x8>; 241 interrupt-parent = <&ipic>; 242 tbi-handle = <&tbi1>; 243 phy-handle = < &phy1 >; 244 fsl,magic-packet; 245 246 mdio@520 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "fsl,gianfar-tbi"; 250 reg = <0x520 0x20>; 251 252 tbi1: tbi-phy@11 { 253 reg = <0x11>; 254 device_type = "tbi-phy"; 255 }; 256 }; 257 }; 258 259 serial0: serial@4500 { 260 cell-index = <0>; 261 device_type = "serial"; 262 compatible = "fsl,ns16550", "ns16550"; 263 reg = <0x4500 0x100>; 264 clock-frequency = <133333333>; 265 interrupts = <9 0x8>; 266 interrupt-parent = <&ipic>; 267 }; 268 269 serial1: serial@4600 { 270 cell-index = <1>; 271 device_type = "serial"; 272 compatible = "fsl,ns16550", "ns16550"; 273 reg = <0x4600 0x100>; 274 clock-frequency = <133333333>; 275 interrupts = <10 0x8>; 276 interrupt-parent = <&ipic>; 277 }; 278 279 crypto@30000 { 280 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", 281 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 282 "fsl,sec2.0"; 283 reg = <0x30000 0x10000>; 284 interrupts = <11 0x8>; 285 interrupt-parent = <&ipic>; 286 fsl,num-channels = <4>; 287 fsl,channel-fifo-len = <24>; 288 fsl,exec-units-mask = <0x97c>; 289 fsl,descriptor-types-mask = <0x3a30abf>; 290 }; 291 292 sata@18000 { 293 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 294 reg = <0x18000 0x1000>; 295 cell-index = <1>; 296 interrupts = <44 0x8>; 297 interrupt-parent = <&ipic>; 298 }; 299 300 sata@19000 { 301 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 302 reg = <0x19000 0x1000>; 303 cell-index = <2>; 304 interrupts = <45 0x8>; 305 interrupt-parent = <&ipic>; 306 }; 307 308 gtm1: timer@500 { 309 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 310 reg = <0x500 0x100>; 311 interrupts = <90 8 78 8 84 8 72 8>; 312 interrupt-parent = <&ipic>; 313 clock-frequency = <133333333>; 314 }; 315 316 timer@600 { 317 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 318 reg = <0x600 0x100>; 319 interrupts = <91 8 79 8 85 8 73 8>; 320 interrupt-parent = <&ipic>; 321 clock-frequency = <133333333>; 322 }; 323 324 /* IPIC 325 * interrupts cell = <intr #, sense> 326 * sense values match linux IORESOURCE_IRQ_* defines: 327 * sense == 8: Level, low assertion 328 * sense == 2: Edge, high-to-low change 329 */ 330 ipic: interrupt-controller@700 { 331 interrupt-controller; 332 #address-cells = <0>; 333 #interrupt-cells = <2>; 334 reg = <0x700 0x100>; 335 device_type = "ipic"; 336 }; 337 338 ipic-msi@7c0 { 339 compatible = "fsl,ipic-msi"; 340 reg = <0x7c0 0x40>; 341 msi-available-ranges = <0 0x100>; 342 interrupts = <0x43 0x8 343 0x4 0x8 344 0x51 0x8 345 0x52 0x8 346 0x56 0x8 347 0x57 0x8 348 0x58 0x8 349 0x59 0x8>; 350 interrupt-parent = < &ipic >; 351 }; 352 353 pmc: power@b00 { 354 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc", 355 "fsl,mpc8349-pmc"; 356 reg = <0xb00 0x100 0xa00 0x100>; 357 interrupts = <80 8>; 358 interrupt-parent = <&ipic>; 359 fsl,mpc8313-wakeup-timer = <>m1>; 360 }; 361 }; 362 363 pci0: pci@e0008500 { 364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 365 interrupt-map = < 366 /* IDSEL 0x0E -mini PCI */ 367 0x7000 0x0 0x0 0x1 &ipic 18 0x8 368 0x7000 0x0 0x0 0x2 &ipic 18 0x8 369 0x7000 0x0 0x0 0x3 &ipic 18 0x8 370 0x7000 0x0 0x0 0x4 &ipic 18 0x8 371 372 /* IDSEL 0x0F -mini PCI */ 373 0x7800 0x0 0x0 0x1 &ipic 17 0x8 374 0x7800 0x0 0x0 0x2 &ipic 17 0x8 375 0x7800 0x0 0x0 0x3 &ipic 17 0x8 376 0x7800 0x0 0x0 0x4 &ipic 17 0x8 377 378 /* IDSEL 0x10 - PCI slot */ 379 0x8000 0x0 0x0 0x1 &ipic 48 0x8 380 0x8000 0x0 0x0 0x2 &ipic 17 0x8 381 0x8000 0x0 0x0 0x3 &ipic 48 0x8 382 0x8000 0x0 0x0 0x4 &ipic 17 0x8>; 383 interrupt-parent = <&ipic>; 384 interrupts = <66 0x8>; 385 bus-range = <0x0 0x0>; 386 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 387 0x42000000 0 0x80000000 0x80000000 0 0x10000000 388 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 389 clock-frequency = <66666666>; 390 #interrupt-cells = <1>; 391 #size-cells = <2>; 392 #address-cells = <3>; 393 reg = <0xe0008500 0x100 /* internal registers */ 394 0xe0008300 0x8>; /* config space access registers */ 395 compatible = "fsl,mpc8349-pci"; 396 device_type = "pci"; 397 }; 398 399 pci1: pcie@e0009000 { 400 #address-cells = <3>; 401 #size-cells = <2>; 402 #interrupt-cells = <1>; 403 device_type = "pci"; 404 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 405 reg = <0xe0009000 0x00001000>; 406 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 407 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 408 bus-range = <0 255>; 409 interrupt-map-mask = <0xf800 0 0 7>; 410 interrupt-map = <0 0 0 1 &ipic 1 8 411 0 0 0 2 &ipic 1 8 412 0 0 0 3 &ipic 1 8 413 0 0 0 4 &ipic 1 8>; 414 clock-frequency = <0>; 415 416 pcie@0 { 417 #address-cells = <3>; 418 #size-cells = <2>; 419 device_type = "pci"; 420 reg = <0 0 0 0 0>; 421 ranges = <0x02000000 0 0xa0000000 422 0x02000000 0 0xa0000000 423 0 0x10000000 424 0x01000000 0 0x00000000 425 0x01000000 0 0x00000000 426 0 0x00800000>; 427 }; 428 }; 429 430 pci2: pcie@e000a000 { 431 #address-cells = <3>; 432 #size-cells = <2>; 433 #interrupt-cells = <1>; 434 device_type = "pci"; 435 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 436 reg = <0xe000a000 0x00001000>; 437 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 438 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; 439 bus-range = <0 255>; 440 interrupt-map-mask = <0xf800 0 0 7>; 441 interrupt-map = <0 0 0 1 &ipic 2 8 442 0 0 0 2 &ipic 2 8 443 0 0 0 3 &ipic 2 8 444 0 0 0 4 &ipic 2 8>; 445 clock-frequency = <0>; 446 447 pcie@0 { 448 #address-cells = <3>; 449 #size-cells = <2>; 450 device_type = "pci"; 451 reg = <0 0 0 0 0>; 452 ranges = <0x02000000 0 0xc0000000 453 0x02000000 0 0xc0000000 454 0 0x10000000 455 0x01000000 0 0x00000000 456 0x01000000 0 0x00000000 457 0 0x00800000>; 458 }; 459 }; 460 461 leds { 462 compatible = "gpio-leds"; 463 464 pwr { 465 gpios = <&mcu_pio 0 0>; 466 default-state = "on"; 467 }; 468 469 hdd { 470 gpios = <&mcu_pio 1 0>; 471 linux,default-trigger = "disk-activity"; 472 }; 473 }; 474}; 475