1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8315E RDB Device Tree Source 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 compatible = "fsl,mpc8315erdb"; 13 model = "MPC8315E-RDB"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 ethernet0 = &enet0; 19 ethernet1 = &enet1; 20 serial0 = &serial0; 21 serial1 = &serial1; 22 pci0 = &pci0; 23 pci1 = &pci1; 24 pci2 = &pci2; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 PowerPC,8315@0 { 32 device_type = "cpu"; 33 reg = <0x0>; 34 d-cache-line-size = <32>; 35 i-cache-line-size = <32>; 36 d-cache-size = <16384>; 37 i-cache-size = <16384>; 38 timebase-frequency = <0>; // from bootloader 39 bus-frequency = <0>; // from bootloader 40 clock-frequency = <0>; // from bootloader 41 }; 42 }; 43 44 memory@0 { 45 device_type = "memory"; 46 reg = <0x00000000 0x08000000>; // 128MB at 0 47 }; 48 49 localbus@e0005000 { 50 #address-cells = <2>; 51 #size-cells = <1>; 52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 53 reg = <0xe0005000 0x1000>; 54 interrupts = <77 IRQ_TYPE_LEVEL_LOW>; 55 interrupt-parent = <&ipic>; 56 57 // CS0 and CS1 are swapped when 58 // booting from nand, but the 59 // addresses are the same. 60 ranges = <0x0 0x0 0xfe000000 0x00800000 61 0x1 0x0 0xe0600000 0x00002000 62 0x2 0x0 0xf0000000 0x00020000 63 0x3 0x0 0xfa000000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x800000>; 70 bank-width = <2>; 71 device-width = <1>; 72 }; 73 74 nand@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8315-fcm-nand", 78 "fsl,elbc-fcm-nand"; 79 reg = <0x1 0x0 0x2000>; 80 81 u-boot@0 { 82 reg = <0x0 0x100000>; 83 read-only; 84 }; 85 86 kernel@100000 { 87 reg = <0x100000 0x300000>; 88 }; 89 fs@400000 { 90 reg = <0x400000 0x1c00000>; 91 }; 92 }; 93 }; 94 95 immr@e0000000 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 device_type = "soc"; 99 compatible = "fsl,mpc8315-immr", "simple-bus"; 100 ranges = <0 0xe0000000 0x00100000>; 101 reg = <0xe0000000 0x00000200>; 102 bus-frequency = <0>; 103 104 watchdog@200 { 105 device_type = "watchdog"; 106 compatible = "mpc83xx_wdt"; 107 reg = <0x200 0x100>; 108 }; 109 110 i2c@3000 { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 cell-index = <0>; 114 compatible = "fsl-i2c"; 115 reg = <0x3000 0x100>; 116 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 117 interrupt-parent = <&ipic>; 118 dfsrr; 119 rtc@68 { 120 compatible = "dallas,ds1339"; 121 reg = <0x68>; 122 }; 123 124 mcu_pio: mcu@a { 125 #gpio-cells = <2>; 126 compatible = "fsl,mc9s08qg8-mpc8315erdb", 127 "fsl,mcu-mpc8349emitx"; 128 reg = <0x0a>; 129 gpio-controller; 130 }; 131 }; 132 133 spi@7000 { 134 cell-index = <0>; 135 compatible = "fsl,spi"; 136 reg = <0x7000 0x1000>; 137 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 138 interrupt-parent = <&ipic>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 mode = "cpu"; 142 }; 143 144 dma@82a8 { 145 #address-cells = <1>; 146 #size-cells = <1>; 147 compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; 148 reg = <0x82a8 4>; 149 ranges = <0 0x8100 0x1a8>; 150 interrupt-parent = <&ipic>; 151 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 152 cell-index = <0>; 153 dma-channel@0 { 154 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 155 reg = <0 0x80>; 156 cell-index = <0>; 157 interrupt-parent = <&ipic>; 158 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 159 }; 160 dma-channel@80 { 161 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 162 reg = <0x80 0x80>; 163 cell-index = <1>; 164 interrupt-parent = <&ipic>; 165 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 166 }; 167 dma-channel@100 { 168 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 169 reg = <0x100 0x80>; 170 cell-index = <2>; 171 interrupt-parent = <&ipic>; 172 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 173 }; 174 dma-channel@180 { 175 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 176 reg = <0x180 0x28>; 177 cell-index = <3>; 178 interrupt-parent = <&ipic>; 179 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 180 }; 181 }; 182 183 usb@23000 { 184 compatible = "fsl-usb2-dr"; 185 reg = <0x23000 0x1000>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 interrupt-parent = <&ipic>; 189 interrupts = <38 IRQ_TYPE_LEVEL_LOW>; 190 phy_type = "utmi"; 191 }; 192 193 enet0: ethernet@24000 { 194 #address-cells = <1>; 195 #size-cells = <1>; 196 cell-index = <0>; 197 device_type = "network"; 198 model = "eTSEC"; 199 compatible = "gianfar"; 200 reg = <0x24000 0x1000>; 201 ranges = <0x0 0x24000 0x1000>; 202 local-mac-address = [ 00 00 00 00 00 00 ]; 203 interrupts = <32 IRQ_TYPE_LEVEL_LOW>, 204 <33 IRQ_TYPE_LEVEL_LOW>, 205 <34 IRQ_TYPE_LEVEL_LOW>; 206 interrupt-parent = <&ipic>; 207 tbi-handle = <&tbi0>; 208 phy-handle = < &phy0 >; 209 fsl,magic-packet; 210 211 mdio@520 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "fsl,gianfar-mdio"; 215 reg = <0x520 0x20>; 216 217 phy0: ethernet-phy@0 { 218 interrupt-parent = <&ipic>; 219 interrupts = <20 0x8>; 220 reg = <0x0>; 221 }; 222 223 phy1: ethernet-phy@1 { 224 interrupt-parent = <&ipic>; 225 interrupts = <19 0x8>; 226 reg = <0x1>; 227 }; 228 229 tbi0: tbi-phy@11 { 230 reg = <0x11>; 231 device_type = "tbi-phy"; 232 }; 233 }; 234 }; 235 236 enet1: ethernet@25000 { 237 #address-cells = <1>; 238 #size-cells = <1>; 239 cell-index = <1>; 240 device_type = "network"; 241 model = "eTSEC"; 242 compatible = "gianfar"; 243 reg = <0x25000 0x1000>; 244 ranges = <0x0 0x25000 0x1000>; 245 local-mac-address = [ 00 00 00 00 00 00 ]; 246 interrupts = <35 IRQ_TYPE_LEVEL_LOW>, 247 <36 IRQ_TYPE_LEVEL_LOW>, 248 <37 IRQ_TYPE_LEVEL_LOW>; 249 interrupt-parent = <&ipic>; 250 tbi-handle = <&tbi1>; 251 phy-handle = < &phy1 >; 252 fsl,magic-packet; 253 254 mdio@520 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 compatible = "fsl,gianfar-tbi"; 258 reg = <0x520 0x20>; 259 260 tbi1: tbi-phy@11 { 261 reg = <0x11>; 262 device_type = "tbi-phy"; 263 }; 264 }; 265 }; 266 267 serial0: serial@4500 { 268 cell-index = <0>; 269 device_type = "serial"; 270 compatible = "fsl,ns16550", "ns16550"; 271 reg = <0x4500 0x100>; 272 clock-frequency = <133333333>; 273 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 274 interrupt-parent = <&ipic>; 275 }; 276 277 serial1: serial@4600 { 278 cell-index = <1>; 279 device_type = "serial"; 280 compatible = "fsl,ns16550", "ns16550"; 281 reg = <0x4600 0x100>; 282 clock-frequency = <133333333>; 283 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 284 interrupt-parent = <&ipic>; 285 }; 286 287 crypto@30000 { 288 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", 289 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 290 "fsl,sec2.0"; 291 reg = <0x30000 0x10000>; 292 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 293 interrupt-parent = <&ipic>; 294 fsl,num-channels = <4>; 295 fsl,channel-fifo-len = <24>; 296 fsl,exec-units-mask = <0x97c>; 297 fsl,descriptor-types-mask = <0x3a30abf>; 298 }; 299 300 sata@18000 { 301 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 302 reg = <0x18000 0x1000>; 303 cell-index = <1>; 304 interrupts = <44 IRQ_TYPE_LEVEL_LOW>; 305 interrupt-parent = <&ipic>; 306 }; 307 308 sata@19000 { 309 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 310 reg = <0x19000 0x1000>; 311 cell-index = <2>; 312 interrupts = <45 IRQ_TYPE_LEVEL_LOW>; 313 interrupt-parent = <&ipic>; 314 }; 315 316 gtm1: timer@500 { 317 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 318 reg = <0x500 0x100>; 319 interrupts = <90 IRQ_TYPE_LEVEL_LOW>, 320 <78 IRQ_TYPE_LEVEL_LOW>, 321 <84 IRQ_TYPE_LEVEL_LOW>, 322 <72 IRQ_TYPE_LEVEL_LOW>; 323 interrupt-parent = <&ipic>; 324 clock-frequency = <133333333>; 325 }; 326 327 timer@600 { 328 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 329 reg = <0x600 0x100>; 330 interrupts = <91 IRQ_TYPE_LEVEL_LOW>, 331 <79 IRQ_TYPE_LEVEL_LOW>, 332 <85 IRQ_TYPE_LEVEL_LOW>, 333 <73 IRQ_TYPE_LEVEL_LOW>; 334 interrupt-parent = <&ipic>; 335 clock-frequency = <133333333>; 336 }; 337 338 /* IPIC 339 * interrupts cell = <intr #, type> 340 */ 341 ipic: interrupt-controller@700 { 342 interrupt-controller; 343 #address-cells = <0>; 344 #interrupt-cells = <2>; 345 reg = <0x700 0x100>; 346 device_type = "ipic"; 347 }; 348 349 ipic-msi@7c0 { 350 compatible = "fsl,ipic-msi"; 351 reg = <0x7c0 0x40>; 352 msi-available-ranges = <0 0x100>; 353 interrupts = <0x43 IRQ_TYPE_LEVEL_LOW 354 0x4 IRQ_TYPE_LEVEL_LOW 355 0x51 IRQ_TYPE_LEVEL_LOW 356 0x52 IRQ_TYPE_LEVEL_LOW 357 0x56 IRQ_TYPE_LEVEL_LOW 358 0x57 IRQ_TYPE_LEVEL_LOW 359 0x58 IRQ_TYPE_LEVEL_LOW 360 0x59 IRQ_TYPE_LEVEL_LOW>; 361 interrupt-parent = < &ipic >; 362 }; 363 364 pmc: power@b00 { 365 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc", 366 "fsl,mpc8349-pmc"; 367 reg = <0xb00 0x100 0xa00 0x100>; 368 interrupts = <80 IRQ_TYPE_LEVEL_LOW>; 369 interrupt-parent = <&ipic>; 370 fsl,mpc8313-wakeup-timer = <>m1>; 371 }; 372 373 gpio: gpio-controller@c00 { 374 compatible = "fsl,mpc8314-gpio"; 375 reg = <0xc00 0x100>; 376 interrupts = <74 IRQ_TYPE_LEVEL_LOW>; 377 interrupt-parent = <&ipic>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 }; 381 }; 382 383 pci0: pci@e0008500 { 384 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 385 interrupt-map = < 386 /* IDSEL 0x0E -mini PCI */ 387 0x7000 0x0 0x0 0x1 &ipic 18 IRQ_TYPE_LEVEL_LOW 388 0x7000 0x0 0x0 0x2 &ipic 18 IRQ_TYPE_LEVEL_LOW 389 0x7000 0x0 0x0 0x3 &ipic 18 IRQ_TYPE_LEVEL_LOW 390 0x7000 0x0 0x0 0x4 &ipic 18 IRQ_TYPE_LEVEL_LOW 391 392 /* IDSEL 0x0F -mini PCI */ 393 0x7800 0x0 0x0 0x1 &ipic 17 IRQ_TYPE_LEVEL_LOW 394 0x7800 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW 395 0x7800 0x0 0x0 0x3 &ipic 17 IRQ_TYPE_LEVEL_LOW 396 0x7800 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW 397 398 /* IDSEL 0x10 - PCI slot */ 399 0x8000 0x0 0x0 0x1 &ipic 48 IRQ_TYPE_LEVEL_LOW 400 0x8000 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW 401 0x8000 0x0 0x0 0x3 &ipic 48 IRQ_TYPE_LEVEL_LOW 402 0x8000 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW>; 403 interrupt-parent = <&ipic>; 404 interrupts = <66 IRQ_TYPE_LEVEL_LOW>; 405 bus-range = <0x0 0x0>; 406 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 407 0x42000000 0 0x80000000 0x80000000 0 0x10000000 408 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 409 clock-frequency = <66666666>; 410 #interrupt-cells = <1>; 411 #size-cells = <2>; 412 #address-cells = <3>; 413 reg = <0xe0008500 0x100 /* internal registers */ 414 0xe0008300 0x8>; /* config space access registers */ 415 compatible = "fsl,mpc8349-pci"; 416 device_type = "pci"; 417 }; 418 419 pci1: pcie@e0009000 { 420 #address-cells = <3>; 421 #size-cells = <2>; 422 #interrupt-cells = <1>; 423 device_type = "pci"; 424 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 425 reg = <0xe0009000 0x00001000>; 426 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 427 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 428 bus-range = <0 255>; 429 interrupt-map-mask = <0xf800 0 0 7>; 430 interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW 431 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW 432 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW 433 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>; 434 clock-frequency = <0>; 435 436 pcie@0 { 437 #address-cells = <3>; 438 #size-cells = <2>; 439 device_type = "pci"; 440 reg = <0 0 0 0 0>; 441 ranges = <0x02000000 0 0xa0000000 442 0x02000000 0 0xa0000000 443 0 0x10000000 444 0x01000000 0 0x00000000 445 0x01000000 0 0x00000000 446 0 0x00800000>; 447 }; 448 }; 449 450 pci2: pcie@e000a000 { 451 #address-cells = <3>; 452 #size-cells = <2>; 453 #interrupt-cells = <1>; 454 device_type = "pci"; 455 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 456 reg = <0xe000a000 0x00001000>; 457 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 458 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; 459 bus-range = <0 255>; 460 interrupt-map-mask = <0xf800 0 0 7>; 461 interrupt-map = <0 0 0 1 &ipic 2 IRQ_TYPE_LEVEL_LOW 462 0 0 0 2 &ipic 2 IRQ_TYPE_LEVEL_LOW 463 0 0 0 3 &ipic 2 IRQ_TYPE_LEVEL_LOW 464 0 0 0 4 &ipic 2 IRQ_TYPE_LEVEL_LOW>; 465 clock-frequency = <0>; 466 467 pcie@0 { 468 #address-cells = <3>; 469 #size-cells = <2>; 470 device_type = "pci"; 471 reg = <0 0 0 0 0>; 472 ranges = <0x02000000 0 0xc0000000 473 0x02000000 0 0xc0000000 474 0 0x10000000 475 0x01000000 0 0x00000000 476 0x01000000 0 0x00000000 477 0 0x00800000>; 478 }; 479 }; 480 481 leds { 482 compatible = "gpio-leds"; 483 484 led-pwr { 485 gpios = <&mcu_pio 0 0>; 486 default-state = "on"; 487 }; 488 489 led-hdd { 490 gpios = <&mcu_pio 1 0>; 491 linux,default-trigger = "disk-activity"; 492 }; 493 }; 494}; 495