1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8315E RDB Device Tree Source 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 compatible = "fsl,mpc8315erdb"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci0 = &pci0; 22 pci1 = &pci1; 23 pci2 = &pci2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8315@0 { 31 device_type = "cpu"; 32 reg = <0x0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <16384>; 36 i-cache-size = <16384>; 37 timebase-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader 40 }; 41 }; 42 43 memory@0 { 44 device_type = "memory"; 45 reg = <0x00000000 0x08000000>; // 128MB at 0 46 }; 47 48 localbus@e0005000 { 49 #address-cells = <2>; 50 #size-cells = <1>; 51 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 52 reg = <0xe0005000 0x1000>; 53 interrupts = <77 IRQ_TYPE_LEVEL_LOW>; 54 interrupt-parent = <&ipic>; 55 56 // CS0 and CS1 are swapped when 57 // booting from nand, but the 58 // addresses are the same. 59 ranges = <0x0 0x0 0xfe000000 0x00800000 60 0x1 0x0 0xe0600000 0x00002000 61 0x2 0x0 0xf0000000 0x00020000 62 0x3 0x0 0xfa000000 0x00008000>; 63 64 flash@0,0 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "cfi-flash"; 68 reg = <0x0 0x0 0x800000>; 69 bank-width = <2>; 70 device-width = <1>; 71 }; 72 73 nand@1,0 { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "fsl,mpc8315-fcm-nand", 77 "fsl,elbc-fcm-nand"; 78 reg = <0x1 0x0 0x2000>; 79 80 u-boot@0 { 81 reg = <0x0 0x100000>; 82 read-only; 83 }; 84 85 kernel@100000 { 86 reg = <0x100000 0x300000>; 87 }; 88 fs@400000 { 89 reg = <0x400000 0x1c00000>; 90 }; 91 }; 92 }; 93 94 immr@e0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 compatible = "fsl,mpc8315-immr", "simple-bus"; 99 ranges = <0 0xe0000000 0x00100000>; 100 reg = <0xe0000000 0x00000200>; 101 bus-frequency = <0>; 102 103 watchdog@200 { 104 device_type = "watchdog"; 105 compatible = "mpc83xx_wdt"; 106 reg = <0x200 0x100>; 107 }; 108 109 i2c@3000 { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 cell-index = <0>; 113 compatible = "fsl-i2c"; 114 reg = <0x3000 0x100>; 115 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 116 interrupt-parent = <&ipic>; 117 dfsrr; 118 rtc@68 { 119 compatible = "dallas,ds1339"; 120 reg = <0x68>; 121 }; 122 123 mcu_pio: mcu@a { 124 #gpio-cells = <2>; 125 compatible = "fsl,mc9s08qg8-mpc8315erdb", 126 "fsl,mcu-mpc8349emitx"; 127 reg = <0x0a>; 128 gpio-controller; 129 }; 130 }; 131 132 spi@7000 { 133 cell-index = <0>; 134 compatible = "fsl,spi"; 135 reg = <0x7000 0x1000>; 136 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 137 interrupt-parent = <&ipic>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 mode = "cpu"; 141 }; 142 143 dma@82a8 { 144 #address-cells = <1>; 145 #size-cells = <1>; 146 compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; 147 reg = <0x82a8 4>; 148 ranges = <0 0x8100 0x1a8>; 149 interrupt-parent = <&ipic>; 150 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 151 cell-index = <0>; 152 dma-channel@0 { 153 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 154 reg = <0 0x80>; 155 cell-index = <0>; 156 interrupt-parent = <&ipic>; 157 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 158 }; 159 dma-channel@80 { 160 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 161 reg = <0x80 0x80>; 162 cell-index = <1>; 163 interrupt-parent = <&ipic>; 164 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 165 }; 166 dma-channel@100 { 167 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 168 reg = <0x100 0x80>; 169 cell-index = <2>; 170 interrupt-parent = <&ipic>; 171 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 172 }; 173 dma-channel@180 { 174 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 175 reg = <0x180 0x28>; 176 cell-index = <3>; 177 interrupt-parent = <&ipic>; 178 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 179 }; 180 }; 181 182 usb@23000 { 183 compatible = "fsl-usb2-dr"; 184 reg = <0x23000 0x1000>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 interrupt-parent = <&ipic>; 188 interrupts = <38 IRQ_TYPE_LEVEL_LOW>; 189 phy_type = "utmi"; 190 }; 191 192 enet0: ethernet@24000 { 193 #address-cells = <1>; 194 #size-cells = <1>; 195 cell-index = <0>; 196 device_type = "network"; 197 model = "eTSEC"; 198 compatible = "gianfar"; 199 reg = <0x24000 0x1000>; 200 ranges = <0x0 0x24000 0x1000>; 201 local-mac-address = [ 00 00 00 00 00 00 ]; 202 interrupts = <32 IRQ_TYPE_LEVEL_LOW>, 203 <33 IRQ_TYPE_LEVEL_LOW>, 204 <34 IRQ_TYPE_LEVEL_LOW>; 205 interrupt-parent = <&ipic>; 206 tbi-handle = <&tbi0>; 207 phy-handle = < &phy0 >; 208 fsl,magic-packet; 209 210 mdio@520 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "fsl,gianfar-mdio"; 214 reg = <0x520 0x20>; 215 216 phy0: ethernet-phy@0 { 217 interrupt-parent = <&ipic>; 218 interrupts = <20 0x8>; 219 reg = <0x0>; 220 }; 221 222 phy1: ethernet-phy@1 { 223 interrupt-parent = <&ipic>; 224 interrupts = <19 0x8>; 225 reg = <0x1>; 226 }; 227 228 tbi0: tbi-phy@11 { 229 reg = <0x11>; 230 device_type = "tbi-phy"; 231 }; 232 }; 233 }; 234 235 enet1: ethernet@25000 { 236 #address-cells = <1>; 237 #size-cells = <1>; 238 cell-index = <1>; 239 device_type = "network"; 240 model = "eTSEC"; 241 compatible = "gianfar"; 242 reg = <0x25000 0x1000>; 243 ranges = <0x0 0x25000 0x1000>; 244 local-mac-address = [ 00 00 00 00 00 00 ]; 245 interrupts = <35 IRQ_TYPE_LEVEL_LOW>, 246 <36 IRQ_TYPE_LEVEL_LOW>, 247 <37 IRQ_TYPE_LEVEL_LOW>; 248 interrupt-parent = <&ipic>; 249 tbi-handle = <&tbi1>; 250 phy-handle = < &phy1 >; 251 fsl,magic-packet; 252 253 mdio@520 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 compatible = "fsl,gianfar-tbi"; 257 reg = <0x520 0x20>; 258 259 tbi1: tbi-phy@11 { 260 reg = <0x11>; 261 device_type = "tbi-phy"; 262 }; 263 }; 264 }; 265 266 serial0: serial@4500 { 267 cell-index = <0>; 268 device_type = "serial"; 269 compatible = "fsl,ns16550", "ns16550"; 270 reg = <0x4500 0x100>; 271 clock-frequency = <133333333>; 272 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 273 interrupt-parent = <&ipic>; 274 }; 275 276 serial1: serial@4600 { 277 cell-index = <1>; 278 device_type = "serial"; 279 compatible = "fsl,ns16550", "ns16550"; 280 reg = <0x4600 0x100>; 281 clock-frequency = <133333333>; 282 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 283 interrupt-parent = <&ipic>; 284 }; 285 286 crypto@30000 { 287 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", 288 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 289 "fsl,sec2.0"; 290 reg = <0x30000 0x10000>; 291 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 292 interrupt-parent = <&ipic>; 293 fsl,num-channels = <4>; 294 fsl,channel-fifo-len = <24>; 295 fsl,exec-units-mask = <0x97c>; 296 fsl,descriptor-types-mask = <0x3a30abf>; 297 }; 298 299 sata@18000 { 300 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 301 reg = <0x18000 0x1000>; 302 cell-index = <1>; 303 interrupts = <44 IRQ_TYPE_LEVEL_LOW>; 304 interrupt-parent = <&ipic>; 305 }; 306 307 sata@19000 { 308 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 309 reg = <0x19000 0x1000>; 310 cell-index = <2>; 311 interrupts = <45 IRQ_TYPE_LEVEL_LOW>; 312 interrupt-parent = <&ipic>; 313 }; 314 315 gtm1: timer@500 { 316 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 317 reg = <0x500 0x100>; 318 interrupts = <90 IRQ_TYPE_LEVEL_LOW>, 319 <78 IRQ_TYPE_LEVEL_LOW>, 320 <84 IRQ_TYPE_LEVEL_LOW>, 321 <72 IRQ_TYPE_LEVEL_LOW>; 322 interrupt-parent = <&ipic>; 323 clock-frequency = <133333333>; 324 }; 325 326 timer@600 { 327 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 328 reg = <0x600 0x100>; 329 interrupts = <91 IRQ_TYPE_LEVEL_LOW>, 330 <79 IRQ_TYPE_LEVEL_LOW>, 331 <85 IRQ_TYPE_LEVEL_LOW>, 332 <73 IRQ_TYPE_LEVEL_LOW>; 333 interrupt-parent = <&ipic>; 334 clock-frequency = <133333333>; 335 }; 336 337 /* IPIC 338 * interrupts cell = <intr #, type> 339 */ 340 ipic: interrupt-controller@700 { 341 interrupt-controller; 342 #address-cells = <0>; 343 #interrupt-cells = <2>; 344 reg = <0x700 0x100>; 345 device_type = "ipic"; 346 }; 347 348 ipic-msi@7c0 { 349 compatible = "fsl,ipic-msi"; 350 reg = <0x7c0 0x40>; 351 msi-available-ranges = <0 0x100>; 352 interrupts = <0x43 IRQ_TYPE_LEVEL_LOW 353 0x4 IRQ_TYPE_LEVEL_LOW 354 0x51 IRQ_TYPE_LEVEL_LOW 355 0x52 IRQ_TYPE_LEVEL_LOW 356 0x56 IRQ_TYPE_LEVEL_LOW 357 0x57 IRQ_TYPE_LEVEL_LOW 358 0x58 IRQ_TYPE_LEVEL_LOW 359 0x59 IRQ_TYPE_LEVEL_LOW>; 360 interrupt-parent = < &ipic >; 361 }; 362 363 pmc: power@b00 { 364 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc", 365 "fsl,mpc8349-pmc"; 366 reg = <0xb00 0x100 0xa00 0x100>; 367 interrupts = <80 IRQ_TYPE_LEVEL_LOW>; 368 interrupt-parent = <&ipic>; 369 fsl,mpc8313-wakeup-timer = <>m1>; 370 }; 371 372 gpio: gpio-controller@c00 { 373 compatible = "fsl,mpc8314-gpio"; 374 reg = <0xc00 0x100>; 375 interrupts = <74 IRQ_TYPE_LEVEL_LOW>; 376 interrupt-parent = <&ipic>; 377 gpio-controller; 378 #gpio-cells = <2>; 379 }; 380 }; 381 382 pci0: pci@e0008500 { 383 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 384 interrupt-map = < 385 /* IDSEL 0x0E -mini PCI */ 386 0x7000 0x0 0x0 0x1 &ipic 18 IRQ_TYPE_LEVEL_LOW 387 0x7000 0x0 0x0 0x2 &ipic 18 IRQ_TYPE_LEVEL_LOW 388 0x7000 0x0 0x0 0x3 &ipic 18 IRQ_TYPE_LEVEL_LOW 389 0x7000 0x0 0x0 0x4 &ipic 18 IRQ_TYPE_LEVEL_LOW 390 391 /* IDSEL 0x0F -mini PCI */ 392 0x7800 0x0 0x0 0x1 &ipic 17 IRQ_TYPE_LEVEL_LOW 393 0x7800 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW 394 0x7800 0x0 0x0 0x3 &ipic 17 IRQ_TYPE_LEVEL_LOW 395 0x7800 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW 396 397 /* IDSEL 0x10 - PCI slot */ 398 0x8000 0x0 0x0 0x1 &ipic 48 IRQ_TYPE_LEVEL_LOW 399 0x8000 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW 400 0x8000 0x0 0x0 0x3 &ipic 48 IRQ_TYPE_LEVEL_LOW 401 0x8000 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW>; 402 interrupt-parent = <&ipic>; 403 interrupts = <66 IRQ_TYPE_LEVEL_LOW>; 404 bus-range = <0x0 0x0>; 405 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 406 0x42000000 0 0x80000000 0x80000000 0 0x10000000 407 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 408 clock-frequency = <66666666>; 409 #interrupt-cells = <1>; 410 #size-cells = <2>; 411 #address-cells = <3>; 412 reg = <0xe0008500 0x100 /* internal registers */ 413 0xe0008300 0x8>; /* config space access registers */ 414 compatible = "fsl,mpc8349-pci"; 415 device_type = "pci"; 416 }; 417 418 pci1: pcie@e0009000 { 419 #address-cells = <3>; 420 #size-cells = <2>; 421 #interrupt-cells = <1>; 422 device_type = "pci"; 423 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 424 reg = <0xe0009000 0x00001000>; 425 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 426 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 427 bus-range = <0 255>; 428 interrupt-map-mask = <0xf800 0 0 7>; 429 interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW 430 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW 431 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW 432 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>; 433 clock-frequency = <0>; 434 435 pcie@0 { 436 #address-cells = <3>; 437 #size-cells = <2>; 438 device_type = "pci"; 439 reg = <0 0 0 0 0>; 440 ranges = <0x02000000 0 0xa0000000 441 0x02000000 0 0xa0000000 442 0 0x10000000 443 0x01000000 0 0x00000000 444 0x01000000 0 0x00000000 445 0 0x00800000>; 446 }; 447 }; 448 449 pci2: pcie@e000a000 { 450 #address-cells = <3>; 451 #size-cells = <2>; 452 #interrupt-cells = <1>; 453 device_type = "pci"; 454 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 455 reg = <0xe000a000 0x00001000>; 456 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 457 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; 458 bus-range = <0 255>; 459 interrupt-map-mask = <0xf800 0 0 7>; 460 interrupt-map = <0 0 0 1 &ipic 2 IRQ_TYPE_LEVEL_LOW 461 0 0 0 2 &ipic 2 IRQ_TYPE_LEVEL_LOW 462 0 0 0 3 &ipic 2 IRQ_TYPE_LEVEL_LOW 463 0 0 0 4 &ipic 2 IRQ_TYPE_LEVEL_LOW>; 464 clock-frequency = <0>; 465 466 pcie@0 { 467 #address-cells = <3>; 468 #size-cells = <2>; 469 device_type = "pci"; 470 reg = <0 0 0 0 0>; 471 ranges = <0x02000000 0 0xc0000000 472 0x02000000 0 0xc0000000 473 0 0x10000000 474 0x01000000 0 0x00000000 475 0x01000000 0 0x00000000 476 0 0x00800000>; 477 }; 478 }; 479 480 leds { 481 compatible = "gpio-leds"; 482 483 led-pwr { 484 gpios = <&mcu_pio 0 0>; 485 default-state = "on"; 486 }; 487 488 led-hdd { 489 gpios = <&mcu_pio 1 0>; 490 linux,default-trigger = "disk-activity"; 491 }; 492 }; 493}; 494