1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8315E RDB Device Tree Source 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 compatible = "fsl,mpc8315erdb"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci0 = &pci0; 22 pci1 = &pci1; 23 pci2 = &pci2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8315@0 { 31 device_type = "cpu"; 32 reg = <0x0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <16384>; 36 i-cache-size = <16384>; 37 timebase-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x00000000 0x08000000>; // 128MB at 0 46 }; 47 48 localbus@e0005000 { 49 #address-cells = <2>; 50 #size-cells = <1>; 51 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 52 reg = <0xe0005000 0x1000>; 53 interrupts = <77 0x8>; 54 interrupt-parent = <&ipic>; 55 56 // CS0 and CS1 are swapped when 57 // booting from nand, but the 58 // addresses are the same. 59 ranges = <0x0 0x0 0xfe000000 0x00800000 60 0x1 0x0 0xe0600000 0x00002000 61 0x2 0x0 0xf0000000 0x00020000 62 0x3 0x0 0xfa000000 0x00008000>; 63 64 flash@0,0 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "cfi-flash"; 68 reg = <0x0 0x0 0x800000>; 69 bank-width = <2>; 70 device-width = <1>; 71 }; 72 73 nand@1,0 { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "fsl,mpc8315-fcm-nand", 77 "fsl,elbc-fcm-nand"; 78 reg = <0x1 0x0 0x2000>; 79 80 u-boot@0 { 81 reg = <0x0 0x100000>; 82 read-only; 83 }; 84 85 kernel@100000 { 86 reg = <0x100000 0x300000>; 87 }; 88 fs@400000 { 89 reg = <0x400000 0x1c00000>; 90 }; 91 }; 92 }; 93 94 immr@e0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 compatible = "fsl,mpc8315-immr", "simple-bus"; 99 ranges = <0 0xe0000000 0x00100000>; 100 reg = <0xe0000000 0x00000200>; 101 bus-frequency = <0>; 102 103 wdt@200 { 104 device_type = "watchdog"; 105 compatible = "mpc83xx_wdt"; 106 reg = <0x200 0x100>; 107 }; 108 109 i2c@3000 { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 cell-index = <0>; 113 compatible = "fsl-i2c"; 114 reg = <0x3000 0x100>; 115 interrupts = <14 0x8>; 116 interrupt-parent = <&ipic>; 117 dfsrr; 118 rtc@68 { 119 compatible = "dallas,ds1339"; 120 reg = <0x68>; 121 }; 122 123 mcu_pio: mcu@a { 124 #gpio-cells = <2>; 125 compatible = "fsl,mc9s08qg8-mpc8315erdb", 126 "fsl,mcu-mpc8349emitx"; 127 reg = <0x0a>; 128 gpio-controller; 129 }; 130 }; 131 132 spi@7000 { 133 cell-index = <0>; 134 compatible = "fsl,spi"; 135 reg = <0x7000 0x1000>; 136 interrupts = <16 0x8>; 137 interrupt-parent = <&ipic>; 138 mode = "cpu"; 139 }; 140 141 dma@82a8 { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; 145 reg = <0x82a8 4>; 146 ranges = <0 0x8100 0x1a8>; 147 interrupt-parent = <&ipic>; 148 interrupts = <71 8>; 149 cell-index = <0>; 150 dma-channel@0 { 151 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 152 reg = <0 0x80>; 153 cell-index = <0>; 154 interrupt-parent = <&ipic>; 155 interrupts = <71 8>; 156 }; 157 dma-channel@80 { 158 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 159 reg = <0x80 0x80>; 160 cell-index = <1>; 161 interrupt-parent = <&ipic>; 162 interrupts = <71 8>; 163 }; 164 dma-channel@100 { 165 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 166 reg = <0x100 0x80>; 167 cell-index = <2>; 168 interrupt-parent = <&ipic>; 169 interrupts = <71 8>; 170 }; 171 dma-channel@180 { 172 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; 173 reg = <0x180 0x28>; 174 cell-index = <3>; 175 interrupt-parent = <&ipic>; 176 interrupts = <71 8>; 177 }; 178 }; 179 180 usb@23000 { 181 compatible = "fsl-usb2-dr"; 182 reg = <0x23000 0x1000>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupt-parent = <&ipic>; 186 interrupts = <38 0x8>; 187 phy_type = "utmi"; 188 }; 189 190 enet0: ethernet@24000 { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 cell-index = <0>; 194 device_type = "network"; 195 model = "eTSEC"; 196 compatible = "gianfar"; 197 reg = <0x24000 0x1000>; 198 ranges = <0x0 0x24000 0x1000>; 199 local-mac-address = [ 00 00 00 00 00 00 ]; 200 interrupts = <32 0x8 33 0x8 34 0x8>; 201 interrupt-parent = <&ipic>; 202 tbi-handle = <&tbi0>; 203 phy-handle = < &phy0 >; 204 fsl,magic-packet; 205 206 mdio@520 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "fsl,gianfar-mdio"; 210 reg = <0x520 0x20>; 211 212 phy0: ethernet-phy@0 { 213 interrupt-parent = <&ipic>; 214 interrupts = <20 0x8>; 215 reg = <0x0>; 216 }; 217 218 phy1: ethernet-phy@1 { 219 interrupt-parent = <&ipic>; 220 interrupts = <19 0x8>; 221 reg = <0x1>; 222 }; 223 224 tbi0: tbi-phy@11 { 225 reg = <0x11>; 226 device_type = "tbi-phy"; 227 }; 228 }; 229 }; 230 231 enet1: ethernet@25000 { 232 #address-cells = <1>; 233 #size-cells = <1>; 234 cell-index = <1>; 235 device_type = "network"; 236 model = "eTSEC"; 237 compatible = "gianfar"; 238 reg = <0x25000 0x1000>; 239 ranges = <0x0 0x25000 0x1000>; 240 local-mac-address = [ 00 00 00 00 00 00 ]; 241 interrupts = <35 0x8 36 0x8 37 0x8>; 242 interrupt-parent = <&ipic>; 243 tbi-handle = <&tbi1>; 244 phy-handle = < &phy1 >; 245 fsl,magic-packet; 246 247 mdio@520 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "fsl,gianfar-tbi"; 251 reg = <0x520 0x20>; 252 253 tbi1: tbi-phy@11 { 254 reg = <0x11>; 255 device_type = "tbi-phy"; 256 }; 257 }; 258 }; 259 260 serial0: serial@4500 { 261 cell-index = <0>; 262 device_type = "serial"; 263 compatible = "fsl,ns16550", "ns16550"; 264 reg = <0x4500 0x100>; 265 clock-frequency = <133333333>; 266 interrupts = <9 0x8>; 267 interrupt-parent = <&ipic>; 268 }; 269 270 serial1: serial@4600 { 271 cell-index = <1>; 272 device_type = "serial"; 273 compatible = "fsl,ns16550", "ns16550"; 274 reg = <0x4600 0x100>; 275 clock-frequency = <133333333>; 276 interrupts = <10 0x8>; 277 interrupt-parent = <&ipic>; 278 }; 279 280 crypto@30000 { 281 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", 282 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 283 "fsl,sec2.0"; 284 reg = <0x30000 0x10000>; 285 interrupts = <11 0x8>; 286 interrupt-parent = <&ipic>; 287 fsl,num-channels = <4>; 288 fsl,channel-fifo-len = <24>; 289 fsl,exec-units-mask = <0x97c>; 290 fsl,descriptor-types-mask = <0x3a30abf>; 291 }; 292 293 sata@18000 { 294 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 295 reg = <0x18000 0x1000>; 296 cell-index = <1>; 297 interrupts = <44 0x8>; 298 interrupt-parent = <&ipic>; 299 }; 300 301 sata@19000 { 302 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 303 reg = <0x19000 0x1000>; 304 cell-index = <2>; 305 interrupts = <45 0x8>; 306 interrupt-parent = <&ipic>; 307 }; 308 309 gtm1: timer@500 { 310 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 311 reg = <0x500 0x100>; 312 interrupts = <90 8 78 8 84 8 72 8>; 313 interrupt-parent = <&ipic>; 314 clock-frequency = <133333333>; 315 }; 316 317 timer@600 { 318 compatible = "fsl,mpc8315-gtm", "fsl,gtm"; 319 reg = <0x600 0x100>; 320 interrupts = <91 8 79 8 85 8 73 8>; 321 interrupt-parent = <&ipic>; 322 clock-frequency = <133333333>; 323 }; 324 325 /* IPIC 326 * interrupts cell = <intr #, sense> 327 * sense values match linux IORESOURCE_IRQ_* defines: 328 * sense == 8: Level, low assertion 329 * sense == 2: Edge, high-to-low change 330 */ 331 ipic: interrupt-controller@700 { 332 interrupt-controller; 333 #address-cells = <0>; 334 #interrupt-cells = <2>; 335 reg = <0x700 0x100>; 336 device_type = "ipic"; 337 }; 338 339 ipic-msi@7c0 { 340 compatible = "fsl,ipic-msi"; 341 reg = <0x7c0 0x40>; 342 msi-available-ranges = <0 0x100>; 343 interrupts = <0x43 0x8 344 0x4 0x8 345 0x51 0x8 346 0x52 0x8 347 0x56 0x8 348 0x57 0x8 349 0x58 0x8 350 0x59 0x8>; 351 interrupt-parent = < &ipic >; 352 }; 353 354 pmc: power@b00 { 355 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc", 356 "fsl,mpc8349-pmc"; 357 reg = <0xb00 0x100 0xa00 0x100>; 358 interrupts = <80 8>; 359 interrupt-parent = <&ipic>; 360 fsl,mpc8313-wakeup-timer = <>m1>; 361 }; 362 363 gpio: gpio-controller@c00 { 364 compatible = "fsl,mpc8314-gpio"; 365 reg = <0xc00 0x100>; 366 interrupts = <74 IRQ_TYPE_LEVEL_LOW>; 367 interrupt-parent = <&ipic>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 }; 371 }; 372 373 pci0: pci@e0008500 { 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 375 interrupt-map = < 376 /* IDSEL 0x0E -mini PCI */ 377 0x7000 0x0 0x0 0x1 &ipic 18 0x8 378 0x7000 0x0 0x0 0x2 &ipic 18 0x8 379 0x7000 0x0 0x0 0x3 &ipic 18 0x8 380 0x7000 0x0 0x0 0x4 &ipic 18 0x8 381 382 /* IDSEL 0x0F -mini PCI */ 383 0x7800 0x0 0x0 0x1 &ipic 17 0x8 384 0x7800 0x0 0x0 0x2 &ipic 17 0x8 385 0x7800 0x0 0x0 0x3 &ipic 17 0x8 386 0x7800 0x0 0x0 0x4 &ipic 17 0x8 387 388 /* IDSEL 0x10 - PCI slot */ 389 0x8000 0x0 0x0 0x1 &ipic 48 0x8 390 0x8000 0x0 0x0 0x2 &ipic 17 0x8 391 0x8000 0x0 0x0 0x3 &ipic 48 0x8 392 0x8000 0x0 0x0 0x4 &ipic 17 0x8>; 393 interrupt-parent = <&ipic>; 394 interrupts = <66 0x8>; 395 bus-range = <0x0 0x0>; 396 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 397 0x42000000 0 0x80000000 0x80000000 0 0x10000000 398 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 399 clock-frequency = <66666666>; 400 #interrupt-cells = <1>; 401 #size-cells = <2>; 402 #address-cells = <3>; 403 reg = <0xe0008500 0x100 /* internal registers */ 404 0xe0008300 0x8>; /* config space access registers */ 405 compatible = "fsl,mpc8349-pci"; 406 device_type = "pci"; 407 }; 408 409 pci1: pcie@e0009000 { 410 #address-cells = <3>; 411 #size-cells = <2>; 412 #interrupt-cells = <1>; 413 device_type = "pci"; 414 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 415 reg = <0xe0009000 0x00001000>; 416 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 417 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 418 bus-range = <0 255>; 419 interrupt-map-mask = <0xf800 0 0 7>; 420 interrupt-map = <0 0 0 1 &ipic 1 8 421 0 0 0 2 &ipic 1 8 422 0 0 0 3 &ipic 1 8 423 0 0 0 4 &ipic 1 8>; 424 clock-frequency = <0>; 425 426 pcie@0 { 427 #address-cells = <3>; 428 #size-cells = <2>; 429 device_type = "pci"; 430 reg = <0 0 0 0 0>; 431 ranges = <0x02000000 0 0xa0000000 432 0x02000000 0 0xa0000000 433 0 0x10000000 434 0x01000000 0 0x00000000 435 0x01000000 0 0x00000000 436 0 0x00800000>; 437 }; 438 }; 439 440 pci2: pcie@e000a000 { 441 #address-cells = <3>; 442 #size-cells = <2>; 443 #interrupt-cells = <1>; 444 device_type = "pci"; 445 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; 446 reg = <0xe000a000 0x00001000>; 447 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 448 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; 449 bus-range = <0 255>; 450 interrupt-map-mask = <0xf800 0 0 7>; 451 interrupt-map = <0 0 0 1 &ipic 2 8 452 0 0 0 2 &ipic 2 8 453 0 0 0 3 &ipic 2 8 454 0 0 0 4 &ipic 2 8>; 455 clock-frequency = <0>; 456 457 pcie@0 { 458 #address-cells = <3>; 459 #size-cells = <2>; 460 device_type = "pci"; 461 reg = <0 0 0 0 0>; 462 ranges = <0x02000000 0 0xc0000000 463 0x02000000 0 0xc0000000 464 0 0x10000000 465 0x01000000 0 0x00000000 466 0x01000000 0 0x00000000 467 0 0x00800000>; 468 }; 469 }; 470 471 leds { 472 compatible = "gpio-leds"; 473 474 pwr { 475 gpios = <&mcu_pio 0 0>; 476 default-state = "on"; 477 }; 478 479 hdd { 480 gpios = <&mcu_pio 1 0>; 481 linux,default-trigger = "disk-activity"; 482 }; 483 }; 484}; 485