1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8313E RDB Device Tree Source 4 * 5 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 model = "MPC8313ERDB"; 13 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 ethernet0 = &enet0; 19 ethernet1 = &enet1; 20 serial0 = &serial0; 21 serial1 = &serial1; 22 pci0 = &pci0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8313@0 { 30 device_type = "cpu"; 31 reg = <0x0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <16384>; 35 i-cache-size = <16384>; 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 39 }; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x00000000 0x08000000>; // 128MB at 0 45 }; 46 47 localbus@e0005000 { 48 #address-cells = <2>; 49 #size-cells = <1>; 50 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; 51 reg = <0xe0005000 0x1000>; 52 interrupts = <77 IRQ_TYPE_LEVEL_LOW>; 53 interrupt-parent = <&ipic>; 54 55 // CS0 and CS1 are swapped when 56 // booting from nand, but the 57 // addresses are the same. 58 ranges = <0x0 0x0 0xfe000000 0x00800000 59 0x1 0x0 0xe2800000 0x00008000 60 0x2 0x0 0xf0000000 0x00020000 61 0x3 0x0 0xfa000000 0x00008000>; 62 63 flash@0,0 { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "cfi-flash"; 67 reg = <0x0 0x0 0x800000>; 68 bank-width = <2>; 69 device-width = <1>; 70 }; 71 72 nand@1,0 { 73 #address-cells = <1>; 74 #size-cells = <1>; 75 compatible = "fsl,mpc8313-fcm-nand", 76 "fsl,elbc-fcm-nand"; 77 reg = <0x1 0x0 0x2000>; 78 79 u-boot@0 { 80 reg = <0x0 0x100000>; 81 read-only; 82 }; 83 84 kernel@100000 { 85 reg = <0x100000 0x300000>; 86 }; 87 88 fs@400000 { 89 reg = <0x400000 0x1c00000>; 90 }; 91 }; 92 }; 93 94 soc8313@e0000000 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 device_type = "soc"; 98 compatible = "simple-bus"; 99 ranges = <0x0 0xe0000000 0x00100000>; 100 reg = <0xe0000000 0x00000200>; 101 bus-frequency = <0>; 102 103 watchdog@200 { 104 device_type = "watchdog"; 105 compatible = "mpc83xx_wdt"; 106 reg = <0x200 0x100>; 107 }; 108 109 sleep-nexus { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 compatible = "simple-bus"; 113 sleep = <&pmc 0x03000000>; 114 ranges; 115 116 i2c@3000 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 cell-index = <0>; 120 compatible = "fsl-i2c"; 121 reg = <0x3000 0x100>; 122 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 123 interrupt-parent = <&ipic>; 124 dfsrr; 125 rtc@68 { 126 compatible = "dallas,ds1339"; 127 reg = <0x68>; 128 }; 129 }; 130 131 crypto@30000 { 132 compatible = "fsl,sec2.2", "fsl,sec2.1", 133 "fsl,sec2.0"; 134 reg = <0x30000 0x10000>; 135 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 136 interrupt-parent = <&ipic>; 137 fsl,num-channels = <1>; 138 fsl,channel-fifo-len = <24>; 139 fsl,exec-units-mask = <0x4c>; 140 fsl,descriptor-types-mask = <0x0122003f>; 141 }; 142 }; 143 144 i2c@3100 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 cell-index = <1>; 148 compatible = "fsl-i2c"; 149 reg = <0x3100 0x100>; 150 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 151 interrupt-parent = <&ipic>; 152 dfsrr; 153 }; 154 155 spi@7000 { 156 cell-index = <0>; 157 compatible = "fsl,spi"; 158 reg = <0x7000 0x1000>; 159 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 160 interrupt-parent = <&ipic>; 161 mode = "cpu"; 162 }; 163 164 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 165 usb@23000 { 166 compatible = "fsl-usb2-dr"; 167 reg = <0x23000 0x1000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 interrupt-parent = <&ipic>; 171 interrupts = <38 IRQ_TYPE_LEVEL_LOW>; 172 phy_type = "utmi_wide"; 173 sleep = <&pmc 0x00300000>; 174 }; 175 176 ptp_clock@24E00 { 177 compatible = "fsl,etsec-ptp"; 178 reg = <0x24E00 0xB0>; 179 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, 180 <13 IRQ_TYPE_LEVEL_LOW>; 181 interrupt-parent = < &ipic >; 182 fsl,tclk-period = <10>; 183 fsl,tmr-prsc = <100>; 184 fsl,tmr-add = <0x999999A4>; 185 fsl,tmr-fiper1 = <0x3B9AC9F6>; 186 fsl,tmr-fiper2 = <0x00018696>; 187 fsl,max-adj = <659999998>; 188 }; 189 190 enet0: ethernet@24000 { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 sleep = <&pmc 0x20000000>; 194 ranges = <0x0 0x24000 0x1000>; 195 196 cell-index = <0>; 197 device_type = "network"; 198 model = "eTSEC"; 199 compatible = "gianfar"; 200 reg = <0x24000 0x1000>; 201 local-mac-address = [ 00 00 00 00 00 00 ]; 202 interrupts = <37 IRQ_TYPE_LEVEL_LOW>, 203 <36 IRQ_TYPE_LEVEL_LOW>, 204 <35 IRQ_TYPE_LEVEL_LOW>; 205 interrupt-parent = <&ipic>; 206 tbi-handle = < &tbi0 >; 207 /* Vitesse 7385 isn't on the MDIO bus */ 208 fixed-link = <1 1 1000 0 0>; 209 fsl,magic-packet; 210 211 mdio@520 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "fsl,gianfar-mdio"; 215 reg = <0x520 0x20>; 216 phy4: ethernet-phy@4 { 217 interrupt-parent = <&ipic>; 218 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 219 reg = <0x4>; 220 }; 221 tbi0: tbi-phy@11 { 222 reg = <0x11>; 223 device_type = "tbi-phy"; 224 }; 225 }; 226 }; 227 228 enet1: ethernet@25000 { 229 #address-cells = <1>; 230 #size-cells = <1>; 231 cell-index = <1>; 232 device_type = "network"; 233 model = "eTSEC"; 234 compatible = "gianfar"; 235 reg = <0x25000 0x1000>; 236 ranges = <0x0 0x25000 0x1000>; 237 local-mac-address = [ 00 00 00 00 00 00 ]; 238 interrupts = <34 IRQ_TYPE_LEVEL_LOW>, 239 <33 IRQ_TYPE_LEVEL_LOW>, 240 <32 IRQ_TYPE_LEVEL_LOW>; 241 interrupt-parent = <&ipic>; 242 tbi-handle = < &tbi1 >; 243 phy-handle = < &phy4 >; 244 sleep = <&pmc 0x10000000>; 245 fsl,magic-packet; 246 247 mdio@520 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "fsl,gianfar-tbi"; 251 reg = <0x520 0x20>; 252 253 tbi1: tbi-phy@11 { 254 reg = <0x11>; 255 device_type = "tbi-phy"; 256 }; 257 }; 258 259 260 }; 261 262 serial0: serial@4500 { 263 cell-index = <0>; 264 device_type = "serial"; 265 compatible = "fsl,ns16550", "ns16550"; 266 reg = <0x4500 0x100>; 267 clock-frequency = <0>; 268 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 269 interrupt-parent = <&ipic>; 270 }; 271 272 serial1: serial@4600 { 273 cell-index = <1>; 274 device_type = "serial"; 275 compatible = "fsl,ns16550", "ns16550"; 276 reg = <0x4600 0x100>; 277 clock-frequency = <0>; 278 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 279 interrupt-parent = <&ipic>; 280 }; 281 282 /* IPIC 283 * interrupts cell = <intr #, type> 284 */ 285 ipic: pic@700 { 286 interrupt-controller; 287 #address-cells = <0>; 288 #interrupt-cells = <2>; 289 reg = <0x700 0x100>; 290 device_type = "ipic"; 291 }; 292 293 pmc: power@b00 { 294 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 295 reg = <0xb00 0x100 0xa00 0x100>; 296 interrupts = <80 IRQ_TYPE_LEVEL_LOW>; 297 interrupt-parent = <&ipic>; 298 fsl,mpc8313-wakeup-timer = <>m1>; 299 300 /* Remove this (or change to "okay") if you have 301 * a REVA3 or later board, if you apply one of the 302 * workarounds listed in section 8.5 of the board 303 * manual, or if you are adapting this device tree 304 * to a different board. 305 */ 306 status = "fail"; 307 }; 308 309 gtm1: timer@500 { 310 compatible = "fsl,mpc8313-gtm", "fsl,gtm"; 311 reg = <0x500 0x100>; 312 interrupts = <90 IRQ_TYPE_LEVEL_LOW>, 313 <78 IRQ_TYPE_LEVEL_LOW>, 314 <84 IRQ_TYPE_LEVEL_LOW>, 315 <72 IRQ_TYPE_LEVEL_LOW>; 316 interrupt-parent = <&ipic>; 317 }; 318 319 timer@600 { 320 compatible = "fsl,mpc8313-gtm", "fsl,gtm"; 321 reg = <0x600 0x100>; 322 interrupts = <91 IRQ_TYPE_LEVEL_LOW>, 323 <79 IRQ_TYPE_LEVEL_LOW>, 324 <85 IRQ_TYPE_LEVEL_LOW>, 325 <73 IRQ_TYPE_LEVEL_LOW>; 326 interrupt-parent = <&ipic>; 327 }; 328 }; 329 330 sleep-nexus { 331 #address-cells = <1>; 332 #size-cells = <1>; 333 compatible = "simple-bus"; 334 sleep = <&pmc 0x00010000>; 335 ranges; 336 337 pci0: pci@e0008500 { 338 cell-index = <1>; 339 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 340 interrupt-map = < 341 /* IDSEL 0x0E -mini PCI */ 342 0x7000 0x0 0x0 0x1 &ipic 18 0x8 343 0x7000 0x0 0x0 0x2 &ipic 18 0x8 344 0x7000 0x0 0x0 0x3 &ipic 18 0x8 345 0x7000 0x0 0x0 0x4 &ipic 18 0x8 346 347 /* IDSEL 0x0F - PCI slot */ 348 0x7800 0x0 0x0 0x1 &ipic 17 0x8 349 0x7800 0x0 0x0 0x2 &ipic 18 0x8 350 0x7800 0x0 0x0 0x3 &ipic 17 0x8 351 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; 352 interrupt-parent = <&ipic>; 353 interrupts = <66 IRQ_TYPE_LEVEL_LOW>; 354 bus-range = <0x0 0x0>; 355 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 356 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 357 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 358 clock-frequency = <66666666>; 359 #interrupt-cells = <1>; 360 #size-cells = <2>; 361 #address-cells = <3>; 362 reg = <0xe0008500 0x100 /* internal registers */ 363 0xe0008300 0x8>; /* config space access registers */ 364 compatible = "fsl,mpc8349-pci"; 365 device_type = "pci"; 366 }; 367 368 dma@82a8 { 369 #address-cells = <1>; 370 #size-cells = <1>; 371 compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; 372 reg = <0xe00082a8 4>; 373 ranges = <0 0xe0008100 0x1a8>; 374 interrupt-parent = <&ipic>; 375 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 376 377 dma-channel@0 { 378 compatible = "fsl,mpc8313-dma-channel", 379 "fsl,elo-dma-channel"; 380 reg = <0 0x28>; 381 interrupt-parent = <&ipic>; 382 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 383 cell-index = <0>; 384 }; 385 386 dma-channel@80 { 387 compatible = "fsl,mpc8313-dma-channel", 388 "fsl,elo-dma-channel"; 389 reg = <0x80 0x28>; 390 interrupt-parent = <&ipic>; 391 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 392 cell-index = <1>; 393 }; 394 395 dma-channel@100 { 396 compatible = "fsl,mpc8313-dma-channel", 397 "fsl,elo-dma-channel"; 398 reg = <0x100 0x28>; 399 interrupt-parent = <&ipic>; 400 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 401 cell-index = <2>; 402 }; 403 404 dma-channel@180 { 405 compatible = "fsl,mpc8313-dma-channel", 406 "fsl,elo-dma-channel"; 407 reg = <0x180 0x28>; 408 interrupt-parent = <&ipic>; 409 interrupts = <71 IRQ_TYPE_LEVEL_LOW>; 410 cell-index = <3>; 411 }; 412 }; 413 }; 414}; 415