1/* 2 * MPC8308RDB Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 compatible = "fsl,mpc8308rdb"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8308@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <16384>; 38 i-cache-size = <16384>; 39 timebase-frequency = <0>; // from bootloader 40 bus-frequency = <0>; // from bootloader 41 clock-frequency = <0>; // from bootloader 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x08000000>; // 128MB at 0 48 }; 49 50 localbus@e0005000 { 51 #address-cells = <2>; 52 #size-cells = <1>; 53 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 54 reg = <0xe0005000 0x1000>; 55 interrupts = <77 0x8>; 56 interrupt-parent = <&ipic>; 57 58 // CS0 and CS1 are swapped when 59 // booting from nand, but the 60 // addresses are the same. 61 ranges = <0x0 0x0 0xfe000000 0x00800000 62 0x1 0x0 0xe0600000 0x00002000 63 0x2 0x0 0xf0000000 0x00020000 64 0x3 0x0 0xfa000000 0x00008000>; 65 66 flash@0,0 { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 compatible = "cfi-flash"; 70 reg = <0x0 0x0 0x800000>; 71 bank-width = <2>; 72 device-width = <1>; 73 74 u-boot@0 { 75 reg = <0x0 0x60000>; 76 read-only; 77 }; 78 env@60000 { 79 reg = <0x60000 0x10000>; 80 }; 81 env1@70000 { 82 reg = <0x70000 0x10000>; 83 }; 84 kernel@80000 { 85 reg = <0x80000 0x200000>; 86 }; 87 dtb@280000 { 88 reg = <0x280000 0x10000>; 89 }; 90 ramdisk@290000 { 91 reg = <0x290000 0x570000>; 92 }; 93 }; 94 95 nand@1,0 { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "fsl,mpc8315-fcm-nand", 99 "fsl,elbc-fcm-nand"; 100 reg = <0x1 0x0 0x2000>; 101 102 jffs2@0 { 103 reg = <0x0 0x2000000>; 104 }; 105 }; 106 }; 107 108 immr@e0000000 { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 device_type = "soc"; 112 compatible = "fsl,mpc8308-immr", "simple-bus"; 113 ranges = <0 0xe0000000 0x00100000>; 114 reg = <0xe0000000 0x00000200>; 115 bus-frequency = <0>; 116 117 i2c@3000 { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 cell-index = <0>; 121 compatible = "fsl-i2c"; 122 reg = <0x3000 0x100>; 123 interrupts = <14 0x8>; 124 interrupt-parent = <&ipic>; 125 dfsrr; 126 rtc@68 { 127 compatible = "dallas,ds1339"; 128 reg = <0x68>; 129 }; 130 }; 131 132 usb@23000 { 133 compatible = "fsl-usb2-dr"; 134 reg = <0x23000 0x1000>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 interrupt-parent = <&ipic>; 138 interrupts = <38 0x8>; 139 dr_mode = "peripheral"; 140 phy_type = "ulpi"; 141 }; 142 143 enet0: ethernet@24000 { 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x24000 0x1000>; 147 148 cell-index = <0>; 149 device_type = "network"; 150 model = "eTSEC"; 151 compatible = "gianfar"; 152 reg = <0x24000 0x1000>; 153 local-mac-address = [ 00 00 00 00 00 00 ]; 154 interrupts = <32 0x8 33 0x8 34 0x8>; 155 interrupt-parent = <&ipic>; 156 tbi-handle = < &tbi0 >; 157 phy-handle = < &phy2 >; 158 fsl,magic-packet; 159 160 mdio@520 { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 compatible = "fsl,gianfar-mdio"; 164 reg = <0x520 0x20>; 165 phy2: ethernet-phy@2 { 166 interrupt-parent = <&ipic>; 167 interrupts = <17 0x8>; 168 reg = <0x2>; 169 }; 170 tbi0: tbi-phy@11 { 171 reg = <0x11>; 172 device_type = "tbi-phy"; 173 }; 174 }; 175 }; 176 177 enet1: ethernet@25000 { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 cell-index = <1>; 181 device_type = "network"; 182 model = "eTSEC"; 183 compatible = "gianfar"; 184 reg = <0x25000 0x1000>; 185 ranges = <0x0 0x25000 0x1000>; 186 local-mac-address = [ 00 00 00 00 00 00 ]; 187 interrupts = <35 0x8 36 0x8 37 0x8>; 188 interrupt-parent = <&ipic>; 189 tbi-handle = < &tbi1 >; 190 /* Vitesse 7385 isn't on the MDIO bus */ 191 fixed-link = <1 1 1000 0 0>; 192 fsl,magic-packet; 193 194 mdio@520 { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 compatible = "fsl,gianfar-tbi"; 198 reg = <0x520 0x20>; 199 200 tbi1: tbi-phy@11 { 201 reg = <0x11>; 202 device_type = "tbi-phy"; 203 }; 204 }; 205 }; 206 207 serial0: serial@4500 { 208 cell-index = <0>; 209 device_type = "serial"; 210 compatible = "fsl,ns16550", "ns16550"; 211 reg = <0x4500 0x100>; 212 clock-frequency = <133333333>; 213 interrupts = <9 0x8>; 214 interrupt-parent = <&ipic>; 215 }; 216 217 serial1: serial@4600 { 218 cell-index = <1>; 219 device_type = "serial"; 220 compatible = "fsl,ns16550", "ns16550"; 221 reg = <0x4600 0x100>; 222 clock-frequency = <133333333>; 223 interrupts = <10 0x8>; 224 interrupt-parent = <&ipic>; 225 }; 226 227 gpio@c00 { 228 #gpio-cells = <2>; 229 device_type = "gpio"; 230 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; 231 reg = <0xc00 0x18>; 232 interrupts = <74 0x8>; 233 interrupt-parent = <&ipic>; 234 gpio-controller; 235 }; 236 237 /* IPIC 238 * interrupts cell = <intr #, sense> 239 * sense values match linux IORESOURCE_IRQ_* defines: 240 * sense == 8: Level, low assertion 241 * sense == 2: Edge, high-to-low change 242 */ 243 ipic: interrupt-controller@700 { 244 compatible = "fsl,ipic"; 245 interrupt-controller; 246 #address-cells = <0>; 247 #interrupt-cells = <2>; 248 reg = <0x700 0x100>; 249 device_type = "ipic"; 250 }; 251 252 ipic-msi@7c0 { 253 compatible = "fsl,ipic-msi"; 254 reg = <0x7c0 0x40>; 255 msi-available-ranges = <0x0 0x100>; 256 interrupts = < 0x43 0x8 257 0x4 0x8 258 0x51 0x8 259 0x52 0x8 260 0x56 0x8 261 0x57 0x8 262 0x58 0x8 263 0x59 0x8 >; 264 interrupt-parent = < &ipic >; 265 }; 266 267 dma@2c000 { 268 compatible = "fsl,mpc8308-dma"; 269 reg = <0x2c000 0x1800>; 270 interrupts = <3 0x8 271 94 0x8>; 272 interrupt-parent = < &ipic >; 273 }; 274 275 }; 276 277 pci0: pcie@e0009000 { 278 #address-cells = <3>; 279 #size-cells = <2>; 280 #interrupt-cells = <1>; 281 device_type = "pci"; 282 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; 283 reg = <0xe0009000 0x00001000 284 0xb0000000 0x01000000>; 285 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 286 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 287 bus-range = <0 0>; 288 interrupt-map-mask = <0xf800 0 0 7>; 289 interrupt-map = <0 0 0 1 &ipic 1 8 290 0 0 0 2 &ipic 1 8 291 0 0 0 3 &ipic 1 8 292 0 0 0 4 &ipic 1 8>; 293 interrupts = <0x1 0x8>; 294 interrupt-parent = <&ipic>; 295 clock-frequency = <0>; 296 297 pcie@0 { 298 #address-cells = <3>; 299 #size-cells = <2>; 300 device_type = "pci"; 301 reg = <0 0 0 0 0>; 302 ranges = <0x02000000 0 0xa0000000 303 0x02000000 0 0xa0000000 304 0 0x10000000 305 0x01000000 0 0x00000000 306 0x01000000 0 0x00000000 307 0 0x00800000>; 308 }; 309 }; 310}; 311