1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8308RDB Device Tree Source 4 * 5 * Copyright 2009 Freescale Semiconductor Inc. 6 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 7 */ 8 9/dts-v1/; 10 11/ { 12 compatible = "fsl,mpc8308rdb"; 13 model = "fsl,mpc8308rdb"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 ethernet0 = &enet0; 19 ethernet1 = &enet1; 20 serial0 = &serial0; 21 serial1 = &serial1; 22 pci0 = &pci0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8308@0 { 30 device_type = "cpu"; 31 reg = <0x0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <16384>; 35 i-cache-size = <16384>; 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 39 }; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x00000000 0x08000000>; // 128MB at 0 45 }; 46 47 localbus@e0005000 { 48 #address-cells = <2>; 49 #size-cells = <1>; 50 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 51 reg = <0xe0005000 0x1000>; 52 interrupts = <77 0x8>; 53 interrupt-parent = <&ipic>; 54 55 // CS0 and CS1 are swapped when 56 // booting from nand, but the 57 // addresses are the same. 58 ranges = <0x0 0x0 0xfe000000 0x00800000 59 0x1 0x0 0xe0600000 0x00002000 60 0x2 0x0 0xf0000000 0x00020000 61 0x3 0x0 0xfa000000 0x00008000>; 62 63 flash@0,0 { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "cfi-flash"; 67 reg = <0x0 0x0 0x800000>; 68 bank-width = <2>; 69 device-width = <1>; 70 71 u-boot@0 { 72 reg = <0x0 0x60000>; 73 read-only; 74 }; 75 env@60000 { 76 reg = <0x60000 0x10000>; 77 }; 78 env1@70000 { 79 reg = <0x70000 0x10000>; 80 }; 81 kernel@80000 { 82 reg = <0x80000 0x200000>; 83 }; 84 dtb@280000 { 85 reg = <0x280000 0x10000>; 86 }; 87 ramdisk@290000 { 88 reg = <0x290000 0x570000>; 89 }; 90 }; 91 92 nand@1,0 { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 compatible = "fsl,mpc8315-fcm-nand", 96 "fsl,elbc-fcm-nand"; 97 reg = <0x1 0x0 0x2000>; 98 99 jffs2@0 { 100 reg = <0x0 0x2000000>; 101 }; 102 }; 103 }; 104 105 immr@e0000000 { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 device_type = "soc"; 109 compatible = "fsl,mpc8308-immr", "simple-bus"; 110 ranges = <0 0xe0000000 0x00100000>; 111 reg = <0xe0000000 0x00000200>; 112 bus-frequency = <0>; 113 114 i2c@3000 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 cell-index = <0>; 118 compatible = "fsl-i2c"; 119 reg = <0x3000 0x100>; 120 interrupts = <14 0x8>; 121 interrupt-parent = <&ipic>; 122 dfsrr; 123 rtc@68 { 124 compatible = "dallas,ds1339"; 125 reg = <0x68>; 126 }; 127 }; 128 129 usb@23000 { 130 compatible = "fsl-usb2-dr"; 131 reg = <0x23000 0x1000>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 interrupt-parent = <&ipic>; 135 interrupts = <38 0x8>; 136 dr_mode = "peripheral"; 137 phy_type = "ulpi"; 138 }; 139 140 enet0: ethernet@24000 { 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0x0 0x24000 0x1000>; 144 145 cell-index = <0>; 146 device_type = "network"; 147 model = "eTSEC"; 148 compatible = "gianfar"; 149 reg = <0x24000 0x1000>; 150 local-mac-address = [ 00 00 00 00 00 00 ]; 151 interrupts = <32 0x8 33 0x8 34 0x8>; 152 interrupt-parent = <&ipic>; 153 tbi-handle = < &tbi0 >; 154 phy-handle = < &phy2 >; 155 fsl,magic-packet; 156 157 mdio@520 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 compatible = "fsl,gianfar-mdio"; 161 reg = <0x520 0x20>; 162 phy2: ethernet-phy@2 { 163 interrupt-parent = <&ipic>; 164 interrupts = <17 0x8>; 165 reg = <0x2>; 166 }; 167 tbi0: tbi-phy@11 { 168 reg = <0x11>; 169 device_type = "tbi-phy"; 170 }; 171 }; 172 }; 173 174 enet1: ethernet@25000 { 175 #address-cells = <1>; 176 #size-cells = <1>; 177 cell-index = <1>; 178 device_type = "network"; 179 model = "eTSEC"; 180 compatible = "gianfar"; 181 reg = <0x25000 0x1000>; 182 ranges = <0x0 0x25000 0x1000>; 183 local-mac-address = [ 00 00 00 00 00 00 ]; 184 interrupts = <35 0x8 36 0x8 37 0x8>; 185 interrupt-parent = <&ipic>; 186 tbi-handle = < &tbi1 >; 187 /* Vitesse 7385 isn't on the MDIO bus */ 188 fixed-link = <1 1 1000 0 0>; 189 fsl,magic-packet; 190 191 mdio@520 { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 compatible = "fsl,gianfar-tbi"; 195 reg = <0x520 0x20>; 196 197 tbi1: tbi-phy@11 { 198 reg = <0x11>; 199 device_type = "tbi-phy"; 200 }; 201 }; 202 }; 203 204 serial0: serial@4500 { 205 cell-index = <0>; 206 device_type = "serial"; 207 compatible = "fsl,ns16550", "ns16550"; 208 reg = <0x4500 0x100>; 209 clock-frequency = <133333333>; 210 interrupts = <9 0x8>; 211 interrupt-parent = <&ipic>; 212 }; 213 214 serial1: serial@4600 { 215 cell-index = <1>; 216 device_type = "serial"; 217 compatible = "fsl,ns16550", "ns16550"; 218 reg = <0x4600 0x100>; 219 clock-frequency = <133333333>; 220 interrupts = <10 0x8>; 221 interrupt-parent = <&ipic>; 222 }; 223 224 gpio@c00 { 225 #gpio-cells = <2>; 226 device_type = "gpio"; 227 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; 228 reg = <0xc00 0x18>; 229 interrupts = <74 0x8>; 230 interrupt-parent = <&ipic>; 231 gpio-controller; 232 }; 233 234 /* IPIC 235 * interrupts cell = <intr #, sense> 236 * sense values match linux IORESOURCE_IRQ_* defines: 237 * sense == 8: Level, low assertion 238 * sense == 2: Edge, high-to-low change 239 */ 240 ipic: interrupt-controller@700 { 241 compatible = "fsl,ipic"; 242 interrupt-controller; 243 #address-cells = <0>; 244 #interrupt-cells = <2>; 245 reg = <0x700 0x100>; 246 device_type = "ipic"; 247 }; 248 249 ipic-msi@7c0 { 250 compatible = "fsl,ipic-msi"; 251 reg = <0x7c0 0x40>; 252 msi-available-ranges = <0x0 0x100>; 253 interrupts = < 0x43 0x8 254 0x4 0x8 255 0x51 0x8 256 0x52 0x8 257 0x56 0x8 258 0x57 0x8 259 0x58 0x8 260 0x59 0x8 >; 261 interrupt-parent = < &ipic >; 262 }; 263 264 dma@2c000 { 265 compatible = "fsl,mpc8308-dma"; 266 reg = <0x2c000 0x1800>; 267 interrupts = <3 0x8 268 94 0x8>; 269 interrupt-parent = < &ipic >; 270 }; 271 272 }; 273 274 pci0: pcie@e0009000 { 275 #address-cells = <3>; 276 #size-cells = <2>; 277 #interrupt-cells = <1>; 278 device_type = "pci"; 279 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; 280 reg = <0xe0009000 0x00001000 281 0xb0000000 0x01000000>; 282 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 283 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 284 bus-range = <0 0>; 285 interrupt-map-mask = <0xf800 0 0 7>; 286 interrupt-map = <0 0 0 1 &ipic 1 8 287 0 0 0 2 &ipic 1 8 288 0 0 0 3 &ipic 1 8 289 0 0 0 4 &ipic 1 8>; 290 interrupts = <0x1 0x8>; 291 interrupt-parent = <&ipic>; 292 clock-frequency = <0>; 293 294 pcie@0 { 295 #address-cells = <3>; 296 #size-cells = <2>; 297 device_type = "pci"; 298 reg = <0 0 0 0 0>; 299 ranges = <0x02000000 0 0xa0000000 300 0x02000000 0 0xa0000000 301 0 0x10000000 302 0x01000000 0 0x00000000 303 0x01000000 0 0x00000000 304 0 0x00800000>; 305 }; 306 }; 307}; 308