1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * mpc8308_p1m Device Tree Source 4 * 5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 6 */ 7 8/dts-v1/; 9 10/ { 11 compatible = "denx,mpc8308_p1m"; 12 model = "denx,mpc8308_p1m"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci0 = &pci0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 PowerPC,8308@0 { 29 device_type = "cpu"; 30 reg = <0x0>; 31 d-cache-line-size = <32>; 32 i-cache-line-size = <32>; 33 d-cache-size = <16384>; 34 i-cache-size = <16384>; 35 timebase-frequency = <0>; // from bootloader 36 bus-frequency = <0>; // from bootloader 37 clock-frequency = <0>; // from bootloader 38 }; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x00000000 0x08000000>; // 128MB at 0 44 }; 45 46 localbus@e0005000 { 47 #address-cells = <2>; 48 #size-cells = <1>; 49 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 50 reg = <0xe0005000 0x1000>; 51 interrupts = <77 0x8>; 52 interrupt-parent = <&ipic>; 53 54 ranges = <0x0 0x0 0xfc000000 0x04000000 55 0x1 0x0 0xfbff0000 0x00008000 56 0x2 0x0 0xfbff8000 0x00008000>; 57 58 flash@0,0 { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 compatible = "cfi-flash"; 62 reg = <0x0 0x0 0x4000000>; 63 bank-width = <2>; 64 device-width = <1>; 65 66 u-boot@0 { 67 reg = <0x0 0x60000>; 68 read-only; 69 }; 70 env@60000 { 71 reg = <0x60000 0x20000>; 72 }; 73 env1@80000 { 74 reg = <0x80000 0x20000>; 75 }; 76 kernel@a0000 { 77 reg = <0xa0000 0x200000>; 78 }; 79 dtb@2a0000 { 80 reg = <0x2a0000 0x20000>; 81 }; 82 ramdisk@2c0000 { 83 reg = <0x2c0000 0x640000>; 84 }; 85 user@700000 { 86 reg = <0x700000 0x3900000>; 87 }; 88 }; 89 90 can@1,0 { 91 compatible = "nxp,sja1000"; 92 reg = <0x1 0x0 0x80>; 93 interrupts = <18 0x8>; 94 interrups-parent = <&ipic>; 95 }; 96 97 cpld@2,0 { 98 compatible = "denx,mpc8308_p1m-cpld"; 99 reg = <0x2 0x0 0x8>; 100 interrupts = <48 0x8>; 101 interrups-parent = <&ipic>; 102 }; 103 }; 104 105 immr@e0000000 { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 device_type = "soc"; 109 compatible = "fsl,mpc8308-immr", "simple-bus"; 110 ranges = <0 0xe0000000 0x00100000>; 111 reg = <0xe0000000 0x00000200>; 112 bus-frequency = <0>; 113 114 i2c@3000 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 compatible = "fsl-i2c"; 118 reg = <0x3000 0x100>; 119 interrupts = <14 0x8>; 120 interrupt-parent = <&ipic>; 121 dfsrr; 122 fram@50 { 123 compatible = "ramtron,24c64", "atmel,24c64"; 124 reg = <0x50>; 125 }; 126 }; 127 128 i2c@3100 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 compatible = "fsl-i2c"; 132 reg = <0x3100 0x100>; 133 interrupts = <15 0x8>; 134 interrupt-parent = <&ipic>; 135 dfsrr; 136 pwm@28 { 137 compatible = "maxim,ds1050"; 138 reg = <0x28>; 139 }; 140 sensor@48 { 141 compatible = "maxim,max6625"; 142 reg = <0x48>; 143 }; 144 sensor@49 { 145 compatible = "maxim,max6625"; 146 reg = <0x49>; 147 }; 148 sensor@4b { 149 compatible = "maxim,max6625"; 150 reg = <0x4b>; 151 }; 152 }; 153 154 usb@23000 { 155 compatible = "fsl-usb2-dr"; 156 reg = <0x23000 0x1000>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 interrupt-parent = <&ipic>; 160 interrupts = <38 0x8>; 161 dr_mode = "peripheral"; 162 phy_type = "ulpi"; 163 }; 164 165 enet0: ethernet@24000 { 166 #address-cells = <1>; 167 #size-cells = <1>; 168 ranges = <0x0 0x24000 0x1000>; 169 170 cell-index = <0>; 171 device_type = "network"; 172 model = "eTSEC"; 173 compatible = "gianfar"; 174 reg = <0x24000 0x1000>; 175 local-mac-address = [ 00 00 00 00 00 00 ]; 176 interrupts = <32 0x8 33 0x8 34 0x8>; 177 interrupt-parent = <&ipic>; 178 phy-handle = < &phy1 >; 179 180 mdio@520 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 compatible = "fsl,gianfar-mdio"; 184 reg = <0x520 0x20>; 185 phy1: ethernet-phy@1 { 186 interrupt-parent = <&ipic>; 187 interrupts = <17 0x8>; 188 reg = <0x1>; 189 }; 190 phy2: ethernet-phy@2 { 191 interrupt-parent = <&ipic>; 192 interrupts = <19 0x8>; 193 reg = <0x2>; 194 }; 195 tbi0: tbi-phy@11 { 196 reg = <0x11>; 197 device_type = "tbi-phy"; 198 }; 199 }; 200 }; 201 202 enet1: ethernet@25000 { 203 #address-cells = <1>; 204 #size-cells = <1>; 205 cell-index = <1>; 206 device_type = "network"; 207 model = "eTSEC"; 208 compatible = "gianfar"; 209 reg = <0x25000 0x1000>; 210 ranges = <0x0 0x25000 0x1000>; 211 local-mac-address = [ 00 00 00 00 00 00 ]; 212 interrupts = <35 0x8 36 0x8 37 0x8>; 213 interrupt-parent = <&ipic>; 214 phy-handle = < &phy2 >; 215 216 mdio@520 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "fsl,gianfar-tbi"; 220 reg = <0x520 0x20>; 221 tbi1: tbi-phy@11 { 222 reg = <0x11>; 223 device_type = "tbi-phy"; 224 }; 225 }; 226 }; 227 228 serial0: serial@4500 { 229 cell-index = <0>; 230 device_type = "serial"; 231 compatible = "fsl,ns16550", "ns16550"; 232 reg = <0x4500 0x100>; 233 clock-frequency = <133333333>; 234 interrupts = <9 0x8>; 235 interrupt-parent = <&ipic>; 236 }; 237 238 serial1: serial@4600 { 239 cell-index = <1>; 240 device_type = "serial"; 241 compatible = "fsl,ns16550", "ns16550"; 242 reg = <0x4600 0x100>; 243 clock-frequency = <133333333>; 244 interrupts = <10 0x8>; 245 interrupt-parent = <&ipic>; 246 }; 247 248 gpio@c00 { 249 #gpio-cells = <2>; 250 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; 251 reg = <0xc00 0x18>; 252 interrupts = <74 0x8>; 253 interrupt-parent = <&ipic>; 254 gpio-controller; 255 }; 256 257 timer@500 { 258 compatible = "fsl,mpc8308-gtm", "fsl,gtm"; 259 reg = <0x500 0x100>; 260 interrupts = <90 8 78 8 84 8 72 8>; 261 interrupt-parent = <&ipic>; 262 clock-frequency = <133333333>; 263 }; 264 265 /* IPIC 266 * interrupts cell = <intr #, sense> 267 * sense values match linux IORESOURCE_IRQ_* defines: 268 * sense == 8: Level, low assertion 269 * sense == 2: Edge, high-to-low change 270 */ 271 ipic: interrupt-controller@700 { 272 compatible = "fsl,ipic"; 273 interrupt-controller; 274 #address-cells = <0>; 275 #interrupt-cells = <2>; 276 reg = <0x700 0x100>; 277 device_type = "ipic"; 278 }; 279 280 ipic-msi@7c0 { 281 compatible = "fsl,ipic-msi"; 282 reg = <0x7c0 0x40>; 283 msi-available-ranges = <0x0 0x100>; 284 interrupts = < 0x43 0x8 285 0x4 0x8 286 0x51 0x8 287 0x52 0x8 288 0x56 0x8 289 0x57 0x8 290 0x58 0x8 291 0x59 0x8 >; 292 interrupt-parent = < &ipic >; 293 }; 294 295 dma@2c000 { 296 compatible = "fsl,mpc8308-dma"; 297 reg = <0x2c000 0x1800>; 298 interrupts = <3 0x8 299 94 0x8>; 300 interrupt-parent = < &ipic >; 301 }; 302 303 }; 304 305 pci0: pcie@e0009000 { 306 #address-cells = <3>; 307 #size-cells = <2>; 308 #interrupt-cells = <1>; 309 device_type = "pci"; 310 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; 311 reg = <0xe0009000 0x00001000 312 0xb0000000 0x01000000>; 313 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 314 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; 315 bus-range = <0 0>; 316 interrupt-map-mask = <0 0 0 0>; 317 interrupt-map = <0 0 0 0 &ipic 1 8>; 318 interrupts = <0x1 0x8>; 319 interrupt-parent = <&ipic>; 320 clock-frequency = <0>; 321 322 pcie@0 { 323 #address-cells = <3>; 324 #size-cells = <2>; 325 device_type = "pci"; 326 reg = <0 0 0 0 0>; 327 ranges = <0x02000000 0 0xa0000000 328 0x02000000 0 0xa0000000 329 0 0x10000000 330 0x01000000 0 0x00000000 331 0x01000000 0 0x00000000 332 0 0x00800000>; 333 }; 334 }; 335}; 336