1/* 2 * STx/Freescale ADS5125 MPC5125 silicon 3 * 4 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. 5 * 6 * Reworked by Matteo Facchinetti (engineering@sirius-es.it) 7 * Copyright (C) 2013 Sirius Electronic Systems 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15/dts-v1/; 16 17/ { 18 model = "mpc5125twr"; // In BSP "mpc5125ads" 19 compatible = "fsl,mpc5125ads", "fsl,mpc5125"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 interrupt-parent = <&ipic>; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 ethernet0 = ð0; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 PowerPC,5125@0 { 35 device_type = "cpu"; 36 reg = <0>; 37 d-cache-line-size = <0x20>; // 32 bytes 38 i-cache-line-size = <0x20>; // 32 bytes 39 d-cache-size = <0x8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K 41 timebase-frequency = <49500000>;// 49.5 MHz (csb/4) 42 bus-frequency = <198000000>; // 198 MHz csb bus 43 clock-frequency = <396000000>; // 396 MHz ppc core 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x10000000>; // 256MB at 0 50 }; 51 52 sram@30000000 { 53 compatible = "fsl,mpc5121-sram"; 54 reg = <0x30000000 0x08000>; // 32K at 0x30000000 55 }; 56 57 soc@80000000 { 58 compatible = "fsl,mpc5121-immr"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 #interrupt-cells = <2>; 62 ranges = <0x0 0x80000000 0x400000>; 63 reg = <0x80000000 0x400000>; 64 bus-frequency = <66000000>; // 66 MHz ips bus 65 66 // IPIC 67 // interrupts cell = <intr #, sense> 68 // sense values match linux IORESOURCE_IRQ_* defines: 69 // sense == 8: Level, low assertion 70 // sense == 2: Edge, high-to-low change 71 // 72 ipic: interrupt-controller@c00 { 73 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 74 interrupt-controller; 75 #address-cells = <0>; 76 #interrupt-cells = <2>; 77 reg = <0xc00 0x100>; 78 }; 79 80 rtc@a00 { // Real time clock 81 compatible = "fsl,mpc5121-rtc"; 82 reg = <0xa00 0x100>; 83 interrupts = <79 0x8 80 0x8>; 84 }; 85 86 reset@e00 { // Reset module 87 compatible = "fsl,mpc5125-reset"; 88 reg = <0xe00 0x100>; 89 }; 90 91 clock@f00 { // Clock control 92 compatible = "fsl,mpc5121-clock"; 93 reg = <0xf00 0x100>; 94 }; 95 96 pmc@1000{ // Power Management Controller 97 compatible = "fsl,mpc5121-pmc"; 98 reg = <0x1000 0x100>; 99 interrupts = <83 0x2>; 100 }; 101 102 gpio0: gpio@1100 { 103 compatible = "fsl,mpc5125-gpio"; 104 reg = <0x1100 0x080>; 105 interrupts = <78 0x8>; 106 }; 107 108 gpio1: gpio@1180 { 109 compatible = "fsl,mpc5125-gpio"; 110 reg = <0x1180 0x080>; 111 interrupts = <86 0x8>; 112 }; 113 114 can@1300 { // CAN rev.2 115 compatible = "fsl,mpc5121-mscan"; 116 interrupts = <12 0x8>; 117 reg = <0x1300 0x80>; 118 }; 119 120 can@1380 { 121 compatible = "fsl,mpc5121-mscan"; 122 interrupts = <13 0x8>; 123 reg = <0x1380 0x80>; 124 }; 125 126 sdhc@1500 { 127 compatible = "fsl,mpc5121-sdhc"; 128 interrupts = <8 0x8>; 129 reg = <0x1500 0x100>; 130 }; 131 132 i2c@1700 { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 136 reg = <0x1700 0x20>; 137 interrupts = <0x9 0x8>; 138 }; 139 140 i2c@1720 { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 144 reg = <0x1720 0x20>; 145 interrupts = <0xa 0x8>; 146 }; 147 148 i2c@1740 { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 152 reg = <0x1740 0x20>; 153 interrupts = <0xb 0x8>; 154 }; 155 156 i2ccontrol@1760 { 157 compatible = "fsl,mpc5121-i2c-ctrl"; 158 reg = <0x1760 0x8>; 159 }; 160 161 diu@2100 { 162 compatible = "fsl,mpc5121-diu"; 163 reg = <0x2100 0x100>; 164 interrupts = <64 0x8>; 165 }; 166 167 mdio@2800 { 168 compatible = "fsl,mpc5121-fec-mdio"; 169 reg = <0x2800 0x800>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 phy0: ethernet-phy@0 { 173 reg = <1>; 174 }; 175 }; 176 177 eth0: ethernet@2800 { 178 compatible = "fsl,mpc5125-fec"; 179 reg = <0x2800 0x800>; 180 local-mac-address = [ 00 00 00 00 00 00 ]; 181 interrupts = <4 0x8>; 182 phy-handle = < &phy0 >; 183 phy-connection-type = "rmii"; 184 }; 185 186 // IO control 187 ioctl@a000 { 188 compatible = "fsl,mpc5125-ioctl"; 189 reg = <0xA000 0x1000>; 190 }; 191 192 usb@3000 { 193 compatible = "fsl,mpc5121-usb2-dr"; 194 reg = <0x3000 0x400>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 interrupts = <43 0x8>; 198 dr_mode = "host"; 199 phy_type = "ulpi"; 200 }; 201 202 // 5125 PSCs are not 52xx or 5121 PSC compatible 203 // PSC1 uart0 aka ttyPSC0 204 serial@11100 { 205 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 206 reg = <0x11100 0x100>; 207 interrupts = <40 0x8>; 208 fsl,rx-fifo-size = <16>; 209 fsl,tx-fifo-size = <16>; 210 }; 211 212 // PSC9 uart1 aka ttyPSC1 213 serial@11900 { 214 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 215 reg = <0x11900 0x100>; 216 interrupts = <40 0x8>; 217 fsl,rx-fifo-size = <16>; 218 fsl,tx-fifo-size = <16>; 219 }; 220 221 pscfifo@11f00 { 222 compatible = "fsl,mpc5121-psc-fifo"; 223 reg = <0x11f00 0x100>; 224 interrupts = <40 0x8>; 225 }; 226 227 dma@14000 { 228 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2" 229 reg = <0x14000 0x1800>; 230 interrupts = <65 0x8>; 231 }; 232 }; 233}; 234