1/* 2 * Freescale Media5200 board Device Tree Source 3 * 4 * Copyright 2009 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * Steven Cavanagh <scavanagh@secretlab.ca> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14/include/ "mpc5200b.dtsi" 15 16&gpt0 { fsl,has-wdt; }; 17 18/ { 19 model = "fsl,media5200"; 20 compatible = "fsl,media5200"; 21 22 aliases { 23 console = &console; 24 ethernet0 = ð0; 25 }; 26 27 chosen { 28 stdout-path = &console; 29 }; 30 31 cpus { 32 PowerPC,5200@0 { 33 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 34 bus-frequency = <132000000>; // 132 MHz 35 clock-frequency = <396000000>; // 396 MHz 36 }; 37 }; 38 39 memory { 40 reg = <0x00000000 0x08000000>; // 128MB RAM 41 }; 42 43 soc5200@f0000000 { 44 bus-frequency = <132000000>;// 132 MHz 45 46 psc@2000 { // PSC1 47 status = "disabled"; 48 }; 49 50 psc@2200 { // PSC2 51 status = "disabled"; 52 }; 53 54 psc@2400 { // PSC3 55 status = "disabled"; 56 }; 57 58 psc@2600 { // PSC4 59 status = "disabled"; 60 }; 61 62 psc@2800 { // PSC5 63 status = "disabled"; 64 }; 65 66 // PSC6 in uart mode 67 console: psc@2c00 { // PSC6 68 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 69 }; 70 71 ethernet@3000 { 72 phy-handle = <&phy0>; 73 }; 74 75 mdio@3000 { 76 phy0: ethernet-phy@0 { 77 reg = <0>; 78 }; 79 }; 80 81 usb@1000 { 82 reg = <0x1000 0x100>; 83 }; 84 }; 85 86 pci@f0000d00 { 87 interrupt-map-mask = <0xf800 0 0 7>; 88 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 89 0xc000 0 0 2 &media5200_fpga 0 3 90 0xc000 0 0 3 &media5200_fpga 0 4 91 0xc000 0 0 4 &media5200_fpga 0 5 92 93 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot 94 0xc800 0 0 2 &media5200_fpga 0 4 95 0xc800 0 0 3 &media5200_fpga 0 5 96 0xc800 0 0 4 &media5200_fpga 0 2 97 98 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI 99 0xd000 0 0 2 &media5200_fpga 0 5 100 101 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 102 >; 103 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 104 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 105 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 106 interrupt-parent = <&mpc5200_pic>; 107 }; 108 109 localbus { 110 ranges = < 0 0 0xfc000000 0x02000000 111 1 0 0xfe000000 0x02000000 112 2 0 0xf0010000 0x00010000 113 3 0 0xf0020000 0x00010000 >; 114 flash@0,0 { 115 compatible = "amd,am29lv28ml", "cfi-flash"; 116 reg = <0 0x0 0x2000000>; // 32 MB 117 bank-width = <4>; // Width in bytes of the flash bank 118 device-width = <2>; // Two devices on each bank 119 }; 120 121 flash@1,0 { 122 compatible = "amd,am29lv28ml", "cfi-flash"; 123 reg = <1 0 0x2000000>; // 32 MB 124 bank-width = <4>; // Width in bytes of the flash bank 125 device-width = <2>; // Two devices on each bank 126 }; 127 128 media5200_fpga: fpga@2,0 { 129 compatible = "fsl,media5200-fpga"; 130 interrupt-controller; 131 #interrupt-cells = <2>; // 0:bank 1:id; no type field 132 reg = <2 0 0x10000>; 133 134 interrupt-parent = <&mpc5200_pic>; 135 interrupts = <0 0 3 // IRQ bank 0 136 1 1 3>; // IRQ bank 1 137 }; 138 139 uart@3,0 { 140 compatible = "ti,tl16c752bpt"; 141 reg = <3 0 0x10000>; 142 interrupt-parent = <&media5200_fpga>; 143 interrupts = <0 0 0 1>; // 2 irqs 144 }; 145 }; 146}; 147