1/* 2 * P5020/5010 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; 37 interrupts = <25 2 0 0>; 38 #address-cells = <2>; 39 #size-cells = <1>; 40}; 41 42/* controller at 0x200000 */ 43&pci0 { 44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 clock-frequency = <33333333>; 50 interrupts = <16 2 1 15>; 51 fsl,iommu-parent = <&pamu0>; 52 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ 53 pcie@0 { 54 reg = <0 0 0 0 0>; 55 #interrupt-cells = <1>; 56 #size-cells = <2>; 57 #address-cells = <3>; 58 device_type = "pci"; 59 interrupts = <16 2 1 15>; 60 interrupt-map-mask = <0xf800 0 0 7>; 61 interrupt-map = < 62 /* IDSEL 0x0 */ 63 0000 0 0 1 &mpic 40 1 0 0 64 0000 0 0 2 &mpic 1 1 0 0 65 0000 0 0 3 &mpic 2 1 0 0 66 0000 0 0 4 &mpic 3 1 0 0 67 >; 68 }; 69}; 70 71/* controller at 0x201000 */ 72&pci1 { 73 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 74 device_type = "pci"; 75 #size-cells = <2>; 76 #address-cells = <3>; 77 bus-range = <0 0xff>; 78 clock-frequency = <33333333>; 79 interrupts = <16 2 1 14>; 80 fsl,iommu-parent = <&pamu0>; 81 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */ 82 pcie@0 { 83 reg = <0 0 0 0 0>; 84 #interrupt-cells = <1>; 85 #size-cells = <2>; 86 #address-cells = <3>; 87 device_type = "pci"; 88 interrupts = <16 2 1 14>; 89 interrupt-map-mask = <0xf800 0 0 7>; 90 interrupt-map = < 91 /* IDSEL 0x0 */ 92 0000 0 0 1 &mpic 41 1 0 0 93 0000 0 0 2 &mpic 5 1 0 0 94 0000 0 0 3 &mpic 6 1 0 0 95 0000 0 0 4 &mpic 7 1 0 0 96 >; 97 }; 98}; 99 100/* controller at 0x202000 */ 101&pci2 { 102 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 103 device_type = "pci"; 104 #size-cells = <2>; 105 #address-cells = <3>; 106 bus-range = <0x0 0xff>; 107 clock-frequency = <33333333>; 108 interrupts = <16 2 1 13>; 109 fsl,iommu-parent = <&pamu0>; 110 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */ 111 pcie@0 { 112 reg = <0 0 0 0 0>; 113 #interrupt-cells = <1>; 114 #size-cells = <2>; 115 #address-cells = <3>; 116 device_type = "pci"; 117 interrupts = <16 2 1 13>; 118 interrupt-map-mask = <0xf800 0 0 7>; 119 interrupt-map = < 120 /* IDSEL 0x0 */ 121 0000 0 0 1 &mpic 42 1 0 0 122 0000 0 0 2 &mpic 9 1 0 0 123 0000 0 0 3 &mpic 10 1 0 0 124 0000 0 0 4 &mpic 11 1 0 0 125 >; 126 }; 127}; 128 129/* controller at 0x203000 */ 130&pci3 { 131 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 132 device_type = "pci"; 133 #size-cells = <2>; 134 #address-cells = <3>; 135 bus-range = <0x0 0xff>; 136 clock-frequency = <33333333>; 137 interrupts = <16 2 1 12>; 138 fsl,iommu-parent = <&pamu0>; 139 fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */ 140 pcie@0 { 141 reg = <0 0 0 0 0>; 142 #interrupt-cells = <1>; 143 #size-cells = <2>; 144 #address-cells = <3>; 145 device_type = "pci"; 146 interrupts = <16 2 1 12>; 147 interrupt-map-mask = <0xf800 0 0 7>; 148 interrupt-map = < 149 /* IDSEL 0x0 */ 150 0000 0 0 1 &mpic 43 1 0 0 151 0000 0 0 2 &mpic 0 1 0 0 152 0000 0 0 3 &mpic 4 1 0 0 153 0000 0 0 4 &mpic 8 1 0 0 154 >; 155 }; 156}; 157 158&rio { 159 compatible = "fsl,srio"; 160 interrupts = <16 2 1 11>; 161 #address-cells = <2>; 162 #size-cells = <2>; 163 fsl,iommu-parent = <&pamu0>; 164 ranges; 165 166 port1 { 167 #address-cells = <2>; 168 #size-cells = <2>; 169 cell-index = <1>; 170 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */ 171 }; 172 173 port2 { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 cell-index = <2>; 177 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */ 178 }; 179}; 180 181&dcsr { 182 #address-cells = <1>; 183 #size-cells = <1>; 184 compatible = "fsl,dcsr", "simple-bus"; 185 186 dcsr-epu@0 { 187 compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu"; 188 interrupts = <52 2 0 0 189 84 2 0 0 190 85 2 0 0>; 191 reg = <0x0 0x1000>; 192 }; 193 dcsr-npc { 194 compatible = "fsl,dcsr-npc"; 195 reg = <0x1000 0x1000 0x1000000 0x8000>; 196 }; 197 dcsr-nxc@2000 { 198 compatible = "fsl,dcsr-nxc"; 199 reg = <0x2000 0x1000>; 200 }; 201 dcsr-corenet { 202 compatible = "fsl,dcsr-corenet"; 203 reg = <0x8000 0x1000 0xB0000 0x1000>; 204 }; 205 dcsr-dpaa@9000 { 206 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa"; 207 reg = <0x9000 0x1000>; 208 }; 209 dcsr-ocn@11000 { 210 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn"; 211 reg = <0x11000 0x1000>; 212 }; 213 dcsr-ddr@12000 { 214 compatible = "fsl,dcsr-ddr"; 215 dev-handle = <&ddr1>; 216 reg = <0x12000 0x1000>; 217 }; 218 dcsr-ddr@13000 { 219 compatible = "fsl,dcsr-ddr"; 220 dev-handle = <&ddr2>; 221 reg = <0x13000 0x1000>; 222 }; 223 dcsr-nal@18000 { 224 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal"; 225 reg = <0x18000 0x1000>; 226 }; 227 dcsr-rcpm@22000 { 228 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm"; 229 reg = <0x22000 0x1000>; 230 }; 231 dcsr-cpu-sb-proxy@40000 { 232 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 233 cpu-handle = <&cpu0>; 234 reg = <0x40000 0x1000>; 235 }; 236 dcsr-cpu-sb-proxy@41000 { 237 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 238 cpu-handle = <&cpu1>; 239 reg = <0x41000 0x1000>; 240 }; 241}; 242 243&soc { 244 #address-cells = <1>; 245 #size-cells = <1>; 246 device_type = "soc"; 247 compatible = "simple-bus"; 248 249 soc-sram-error { 250 compatible = "fsl,soc-sram-error"; 251 interrupts = <16 2 1 29>; 252 }; 253 254 corenet-law@0 { 255 compatible = "fsl,corenet-law"; 256 reg = <0x0 0x1000>; 257 fsl,num-laws = <32>; 258 }; 259 260 ddr1: memory-controller@8000 { 261 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 262 reg = <0x8000 0x1000>; 263 interrupts = <16 2 1 23>; 264 }; 265 266 ddr2: memory-controller@9000 { 267 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller"; 268 reg = <0x9000 0x1000>; 269 interrupts = <16 2 1 22>; 270 }; 271 272 cpc: l3-cache-controller@10000 { 273 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 274 reg = <0x10000 0x1000 275 0x11000 0x1000>; 276 interrupts = <16 2 1 27 277 16 2 1 26>; 278 }; 279 280 corenet-cf@18000 { 281 compatible = "fsl,corenet-cf"; 282 reg = <0x18000 0x1000>; 283 interrupts = <16 2 1 31>; 284 fsl,ccf-num-csdids = <32>; 285 fsl,ccf-num-snoopids = <32>; 286 }; 287 288 iommu@20000 { 289 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 290 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */ 291 ranges = <0 0x20000 0x4000>; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 interrupts = < 295 24 2 0 0 296 16 2 1 30>; 297 298 pamu0: pamu@0 { 299 reg = <0 0x1000>; 300 fsl,primary-cache-geometry = <32 1>; 301 fsl,secondary-cache-geometry = <128 2>; 302 }; 303 304 pamu1: pamu@1000 { 305 reg = <0x1000 0x1000>; 306 fsl,primary-cache-geometry = <32 1>; 307 fsl,secondary-cache-geometry = <128 2>; 308 }; 309 310 pamu2: pamu@2000 { 311 reg = <0x2000 0x1000>; 312 fsl,primary-cache-geometry = <32 1>; 313 fsl,secondary-cache-geometry = <128 2>; 314 }; 315 316 pamu3: pamu@3000 { 317 reg = <0x3000 0x1000>; 318 fsl,primary-cache-geometry = <32 1>; 319 fsl,secondary-cache-geometry = <128 2>; 320 }; 321 }; 322 323/include/ "qoriq-mpic.dtsi" 324 325 guts: global-utilities@e0000 { 326 compatible = "fsl,qoriq-device-config-1.0"; 327 reg = <0xe0000 0xe00>; 328 fsl,has-rstcr; 329 #sleep-cells = <1>; 330 fsl,liodn-bits = <12>; 331 }; 332 333 pins: global-utilities@e0e00 { 334 compatible = "fsl,qoriq-pin-control-1.0"; 335 reg = <0xe0e00 0x200>; 336 #sleep-cells = <2>; 337 }; 338 339 clockgen: global-utilities@e1000 { 340 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 341 reg = <0xe1000 0x1000>; 342 clock-frequency = <0>; 343 }; 344 345 rcpm: global-utilities@e2000 { 346 compatible = "fsl,qoriq-rcpm-1.0"; 347 reg = <0xe2000 0x1000>; 348 #sleep-cells = <1>; 349 }; 350 351 sfp: sfp@e8000 { 352 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0"; 353 reg = <0xe8000 0x1000>; 354 }; 355 356 serdes: serdes@ea000 { 357 compatible = "fsl,p5020-serdes"; 358 reg = <0xea000 0x1000>; 359 }; 360 361/include/ "qoriq-dma-0.dtsi" 362 dma@100300 { 363 fsl,iommu-parent = <&pamu0>; 364 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ 365 }; 366 367/include/ "qoriq-dma-1.dtsi" 368 dma@101300 { 369 fsl,iommu-parent = <&pamu0>; 370 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ 371 }; 372 373/include/ "qoriq-espi-0.dtsi" 374 spi@110000 { 375 fsl,espi-num-chipselects = <4>; 376 }; 377 378/include/ "qoriq-esdhc-0.dtsi" 379 sdhc@114000 { 380 fsl,iommu-parent = <&pamu1>; 381 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 382 sdhci,auto-cmd12; 383 }; 384 385/include/ "qoriq-i2c-0.dtsi" 386/include/ "qoriq-i2c-1.dtsi" 387/include/ "qoriq-duart-0.dtsi" 388/include/ "qoriq-duart-1.dtsi" 389/include/ "qoriq-gpio-0.dtsi" 390/include/ "qoriq-usb2-mph-0.dtsi" 391 usb0: usb@210000 { 392 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 393 fsl,iommu-parent = <&pamu1>; 394 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 395 phy_type = "utmi"; 396 port0; 397 }; 398 399/include/ "qoriq-usb2-dr-0.dtsi" 400 usb1: usb@211000 { 401 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 402 fsl,iommu-parent = <&pamu1>; 403 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ 404 dr_mode = "host"; 405 phy_type = "utmi"; 406 }; 407 408/include/ "qoriq-sata2-0.dtsi" 409 sata@220000 { 410 fsl,iommu-parent = <&pamu1>; 411 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ 412 }; 413 414/include/ "qoriq-sata2-1.dtsi" 415 sata@221000 { 416 fsl,iommu-parent = <&pamu1>; 417 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ 418 }; 419/include/ "qoriq-sec4.2-0.dtsi" 420 crypto@300000 { 421 fsl,iommu-parent = <&pamu1>; 422 }; 423 424/include/ "qoriq-raid1.0-0.dtsi" 425 raideng@320000 { 426 fsl,iommu-parent = <&pamu1>; 427 }; 428}; 429