1/* 2 * P5020DS Device Tree Source 3 * 4 * Copyright 2010 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p5020si-pre.dtsi" 36 37/ { 38 model = "fsl,P5020DS"; 39 compatible = "fsl,P5020DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii_0 = &phy_rgmii_0; 46 phy_rgmii_1 = &phy_rgmii_1; 47 phy_sgmii_1c = &phy_sgmii_1c; 48 phy_sgmii_1d = &phy_sgmii_1d; 49 phy_sgmii_1e = &phy_sgmii_1e; 50 phy_sgmii_1f = &phy_sgmii_1f; 51 phy_xgmii_1 = &phy_xgmii_1; 52 phy_xgmii_2 = &phy_xgmii_2; 53 emi1_rgmii = &hydra_mdio_rgmii; 54 emi1_sgmii = &hydra_mdio_sgmii; 55 emi2_xgmii = &hydra_mdio_xgmii; 56 }; 57 58 memory { 59 device_type = "memory"; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 bman_fbpr: bman-fbpr { 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 70 }; 71 qman_fqd: qman-fqd { 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 74 }; 75 qman_pfdr: qman-pfdr { 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 78 }; 79 }; 80 81 dcsr: dcsr@f00000000 { 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 83 }; 84 85 bportals: bman-portals@ff4000000 { 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 87 }; 88 89 qportals: qman-portals@ff4200000 { 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 91 }; 92 93 soc: soc@ffe000000 { 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 95 reg = <0xf 0xfe000000 0 0x00001000>; 96 spi@110000 { 97 flash@0 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 101 reg = <0>; 102 spi-max-frequency = <40000000>; /* input clock */ 103 partition@u-boot { 104 label = "u-boot"; 105 reg = <0x00000000 0x00100000>; 106 read-only; 107 }; 108 partition@kernel { 109 label = "kernel"; 110 reg = <0x00100000 0x00500000>; 111 read-only; 112 }; 113 partition@dtb { 114 label = "dtb"; 115 reg = <0x00600000 0x00100000>; 116 read-only; 117 }; 118 partition@fs { 119 label = "file system"; 120 reg = <0x00700000 0x00900000>; 121 }; 122 }; 123 }; 124 125 i2c@118100 { 126 eeprom@51 { 127 compatible = "at24,24c256"; 128 reg = <0x51>; 129 }; 130 eeprom@52 { 131 compatible = "at24,24c256"; 132 reg = <0x52>; 133 }; 134 }; 135 136 i2c@119100 { 137 rtc@68 { 138 compatible = "dallas,ds3232"; 139 reg = <0x68>; 140 interrupts = <0x1 0x1 0 0>; 141 }; 142 ina220@40 { 143 compatible = "ti,ina220"; 144 reg = <0x40>; 145 shunt-resistor = <1000>; 146 }; 147 ina220@41 { 148 compatible = "ti,ina220"; 149 reg = <0x41>; 150 shunt-resistor = <1000>; 151 }; 152 ina220@44 { 153 compatible = "ti,ina220"; 154 reg = <0x44>; 155 shunt-resistor = <1000>; 156 }; 157 ina220@45 { 158 compatible = "ti,ina220"; 159 reg = <0x45>; 160 shunt-resistor = <1000>; 161 }; 162 adt7461@4c { 163 compatible = "adi,adt7461"; 164 reg = <0x4c>; 165 }; 166 }; 167 168 fman@400000 { 169 ethernet@e0000 { 170 phy-handle = <&phy_sgmii_1c>; 171 phy-connection-type = "sgmii"; 172 }; 173 174 ethernet@e2000 { 175 phy-handle = <&phy_sgmii_1d>; 176 phy-connection-type = "sgmii"; 177 }; 178 179 ethernet@e4000 { 180 phy-handle = <&phy_sgmii_1e>; 181 phy-connection-type = "sgmii"; 182 }; 183 184 ethernet@e6000 { 185 phy-handle = <&phy_sgmii_1f>; 186 phy-connection-type = "sgmii"; 187 }; 188 189 ethernet@e8000 { 190 phy-handle = <&phy_rgmii_1>; 191 phy-connection-type = "rgmii"; 192 }; 193 194 ethernet@f0000 { 195 phy-handle = <&phy_xgmii_1>; 196 phy-connection-type = "xgmii"; 197 }; 198 199 hydra_mdio_xgmii: mdio@f1000 { 200 status = "disabled"; 201 202 phy_xgmii_1: ethernet-phy@4 { 203 compatible = "ethernet-phy-ieee802.3-c45"; 204 reg = <0x4>; 205 }; 206 207 phy_xgmii_2: ethernet-phy@0 { 208 compatible = "ethernet-phy-ieee802.3-c45"; 209 reg = <0x0>; 210 }; 211 }; 212 }; 213 }; 214 215 rio: rapidio@ffe0c0000 { 216 reg = <0xf 0xfe0c0000 0 0x11000>; 217 218 port1 { 219 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 220 }; 221 port2 { 222 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 223 }; 224 }; 225 226 lbc: localbus@ffe124000 { 227 reg = <0xf 0xfe124000 0 0x1000>; 228 ranges = <0 0 0xf 0xe8000000 0x08000000 229 2 0 0xf 0xffa00000 0x00040000 230 3 0 0xf 0xffdf0000 0x00008000>; 231 232 flash@0,0 { 233 compatible = "cfi-flash"; 234 reg = <0 0 0x08000000>; 235 bank-width = <2>; 236 device-width = <2>; 237 }; 238 239 nand@2,0 { 240 #address-cells = <1>; 241 #size-cells = <1>; 242 compatible = "fsl,elbc-fcm-nand"; 243 reg = <0x2 0x0 0x40000>; 244 245 partition@0 { 246 label = "NAND U-Boot Image"; 247 reg = <0x0 0x02000000>; 248 read-only; 249 }; 250 251 partition@2000000 { 252 label = "NAND Root File System"; 253 reg = <0x02000000 0x10000000>; 254 }; 255 256 partition@12000000 { 257 label = "NAND Compressed RFS Image"; 258 reg = <0x12000000 0x08000000>; 259 }; 260 261 partition@1a000000 { 262 label = "NAND Linux Kernel Image"; 263 reg = <0x1a000000 0x04000000>; 264 }; 265 266 partition@1e000000 { 267 label = "NAND DTB Image"; 268 reg = <0x1e000000 0x01000000>; 269 }; 270 271 partition@1f000000 { 272 label = "NAND Writable User area"; 273 reg = <0x1f000000 0x21000000>; 274 }; 275 }; 276 277 board-control@3,0 { 278 #address-cells = <1>; 279 #size-cells = <1>; 280 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; 281 reg = <3 0 0x30>; 282 ranges = <0 3 0 0x30>; 283 284 mdio-mux-emi1 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 compatible = "mdio-mux-mmioreg", "mdio-mux"; 288 mdio-parent-bus = <&mdio0>; 289 reg = <9 1>; 290 mux-mask = <0x78>; 291 292 hydra_mdio_rgmii: rgmii-mdio@8 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 reg = <8>; 296 status = "disabled"; 297 298 phy_rgmii_0: ethernet-phy@0 { 299 reg = <0x0>; 300 }; 301 302 phy_rgmii_1: ethernet-phy@1 { 303 reg = <0x1>; 304 }; 305 }; 306 307 hydra_mdio_sgmii: sgmii-mdio@28 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <0x28>; 311 status = "disabled"; 312 313 phy_sgmii_1c: ethernet-phy@1c { 314 reg = <0x1c>; 315 }; 316 317 phy_sgmii_1d: ethernet-phy@1d { 318 reg = <0x1d>; 319 }; 320 321 phy_sgmii_1e: ethernet-phy@1e { 322 reg = <0x1e>; 323 }; 324 325 phy_sgmii_1f: ethernet-phy@1f { 326 reg = <0x1f>; 327 }; 328 }; 329 }; 330 }; 331 }; 332 333 pci0: pcie@ffe200000 { 334 reg = <0xf 0xfe200000 0 0x1000>; 335 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 336 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 337 pcie@0 { 338 ranges = <0x02000000 0 0xe0000000 339 0x02000000 0 0xe0000000 340 0 0x20000000 341 342 0x01000000 0 0x00000000 343 0x01000000 0 0x00000000 344 0 0x00010000>; 345 }; 346 }; 347 348 pci1: pcie@ffe201000 { 349 reg = <0xf 0xfe201000 0 0x1000>; 350 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 351 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 352 pcie@0 { 353 ranges = <0x02000000 0 0xe0000000 354 0x02000000 0 0xe0000000 355 0 0x20000000 356 357 0x01000000 0 0x00000000 358 0x01000000 0 0x00000000 359 0 0x00010000>; 360 }; 361 }; 362 363 pci2: pcie@ffe202000 { 364 reg = <0xf 0xfe202000 0 0x1000>; 365 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 366 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 367 pcie@0 { 368 ranges = <0x02000000 0 0xe0000000 369 0x02000000 0 0xe0000000 370 0 0x20000000 371 372 0x01000000 0 0x00000000 373 0x01000000 0 0x00000000 374 0 0x00010000>; 375 }; 376 }; 377 378 pci3: pcie@ffe203000 { 379 reg = <0xf 0xfe203000 0 0x1000>; 380 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 381 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 382 pcie@0 { 383 ranges = <0x02000000 0 0xe0000000 384 0x02000000 0 0xe0000000 385 0 0x20000000 386 387 0x01000000 0 0x00000000 388 0x01000000 0 0x00000000 389 0 0x00010000>; 390 }; 391 }; 392}; 393 394/include/ "p5020si-post.dtsi" 395