1/* 2 * P4080DS Device Tree Source 3 * 4 * Copyright 2009 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/include/ "p4080si-pre.dtsi" 36 37/ { 38 model = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 phy_rgmii = &phyrgmii; 46 phy5_slot3 = &phy5slot3; 47 phy6_slot3 = &phy6slot3; 48 phy7_slot3 = &phy7slot3; 49 phy8_slot3 = &phy8slot3; 50 emi1_slot3 = &p4080mdio2; 51 emi1_slot4 = &p4080mdio1; 52 emi1_slot5 = &p4080mdio3; 53 emi1_rgmii = &p4080mdio0; 54 emi2_slot4 = &p4080xmdio1; 55 emi2_slot5 = &p4080xmdio3; 56 }; 57 58 memory { 59 device_type = "memory"; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 bman_fbpr: bman-fbpr { 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 70 }; 71 qman_fqd: qman-fqd { 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 74 }; 75 qman_pfdr: qman-pfdr { 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 78 }; 79 }; 80 81 dcsr: dcsr@f00000000 { 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 83 }; 84 85 bportals: bman-portals@ff4000000 { 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 87 }; 88 89 qportals: qman-portals@ff4200000 { 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 91 }; 92 93 soc: soc@ffe000000 { 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 95 reg = <0xf 0xfe000000 0 0x00001000>; 96 97 spi@110000 { 98 flash@0 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 102 reg = <0>; 103 spi-max-frequency = <40000000>; /* input clock */ 104 partition@u-boot { 105 label = "u-boot"; 106 reg = <0x00000000 0x00100000>; 107 read-only; 108 }; 109 partition@kernel { 110 label = "kernel"; 111 reg = <0x00100000 0x00500000>; 112 read-only; 113 }; 114 partition@dtb { 115 label = "dtb"; 116 reg = <0x00600000 0x00100000>; 117 read-only; 118 }; 119 partition@fs { 120 label = "file system"; 121 reg = <0x00700000 0x00900000>; 122 }; 123 }; 124 }; 125 126 i2c@118100 { 127 eeprom@51 { 128 compatible = "atmel,spd"; 129 reg = <0x51>; 130 }; 131 eeprom@52 { 132 compatible = "atmel,spd"; 133 reg = <0x52>; 134 }; 135 rtc@68 { 136 compatible = "dallas,ds3232"; 137 reg = <0x68>; 138 interrupts = <0x1 0x1 0 0>; 139 }; 140 adt7461@4c { 141 compatible = "adi,adt7461"; 142 reg = <0x4c>; 143 }; 144 }; 145 146 i2c@118000 { 147 zl2006@21 { 148 compatible = "zl2006"; 149 reg = <0x21>; 150 }; 151 zl2006@22 { 152 compatible = "zl2006"; 153 reg = <0x22>; 154 }; 155 zl2006@23 { 156 compatible = "zl2006"; 157 reg = <0x23>; 158 }; 159 zl2006@24 { 160 compatible = "zl2006"; 161 reg = <0x24>; 162 }; 163 eeprom@50 { 164 compatible = "atmel,24c64"; 165 reg = <0x50>; 166 }; 167 eeprom@55 { 168 compatible = "atmel,24c64"; 169 reg = <0x55>; 170 }; 171 eeprom@56 { 172 compatible = "atmel,24c64"; 173 reg = <0x56>; 174 }; 175 eeprom@57 { 176 compatible = "atmel,24c02"; 177 reg = <0x57>; 178 }; 179 }; 180 181 i2c@119100 { 182 /* 0x6E: ICS9FG108 */ 183 }; 184 185 usb0: usb@210000 { 186 phy_type = "ulpi"; 187 }; 188 189 usb1: usb@211000 { 190 dr_mode = "host"; 191 phy_type = "ulpi"; 192 }; 193 194 fman@400000 { 195 ethernet@e0000 { 196 phy-handle = <&phy0>; 197 phy-connection-type = "sgmii"; 198 }; 199 200 ethernet@e2000 { 201 phy-handle = <&phy1>; 202 phy-connection-type = "sgmii"; 203 }; 204 205 ethernet@e4000 { 206 phy-handle = <&phy2>; 207 phy-connection-type = "sgmii"; 208 }; 209 210 ethernet@e6000 { 211 phy-handle = <&phy3>; 212 phy-connection-type = "sgmii"; 213 }; 214 215 ethernet@f0000 { 216 phy-handle = <&phy10>; 217 phy-connection-type = "xgmii"; 218 }; 219 }; 220 221 fman@500000 { 222 ethernet@e0000 { 223 phy-handle = <&phy5>; 224 phy-connection-type = "sgmii"; 225 }; 226 227 ethernet@e2000 { 228 phy-handle = <&phy6>; 229 phy-connection-type = "sgmii"; 230 }; 231 232 ethernet@e4000 { 233 phy-handle = <&phy7>; 234 phy-connection-type = "sgmii"; 235 }; 236 237 ethernet@e6000 { 238 phy-handle = <&phy8>; 239 phy-connection-type = "sgmii"; 240 }; 241 242 ethernet@f0000 { 243 phy-handle = <&phy11>; 244 phy-connection-type = "xgmii"; 245 }; 246 }; 247 }; 248 249 rio: rapidio@ffe0c0000 { 250 reg = <0xf 0xfe0c0000 0 0x11000>; 251 252 port1 { 253 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 254 }; 255 port2 { 256 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 257 }; 258 }; 259 260 lbc: localbus@ffe124000 { 261 reg = <0xf 0xfe124000 0 0x1000>; 262 ranges = <0 0 0xf 0xe8000000 0x08000000 263 3 0 0xf 0xffdf0000 0x00008000>; 264 265 flash@0,0 { 266 compatible = "cfi-flash"; 267 reg = <0 0 0x08000000>; 268 bank-width = <2>; 269 device-width = <2>; 270 }; 271 272 board-control@3,0 { 273 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; 274 reg = <3 0 0x30>; 275 }; 276 }; 277 278 pci0: pcie@ffe200000 { 279 reg = <0xf 0xfe200000 0 0x1000>; 280 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 281 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 282 pcie@0 { 283 ranges = <0x02000000 0 0xe0000000 284 0x02000000 0 0xe0000000 285 0 0x20000000 286 287 0x01000000 0 0x00000000 288 0x01000000 0 0x00000000 289 0 0x00010000>; 290 }; 291 }; 292 293 pci1: pcie@ffe201000 { 294 reg = <0xf 0xfe201000 0 0x1000>; 295 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 296 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 297 pcie@0 { 298 ranges = <0x02000000 0 0xe0000000 299 0x02000000 0 0xe0000000 300 0 0x20000000 301 302 0x01000000 0 0x00000000 303 0x01000000 0 0x00000000 304 0 0x00010000>; 305 }; 306 }; 307 308 pci2: pcie@ffe202000 { 309 reg = <0xf 0xfe202000 0 0x1000>; 310 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 311 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 312 pcie@0 { 313 ranges = <0x02000000 0 0xe0000000 314 0x02000000 0 0xe0000000 315 0 0x20000000 316 317 0x01000000 0 0x00000000 318 0x01000000 0 0x00000000 319 0 0x00010000>; 320 }; 321 }; 322 323 mdio-mux-emi1 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "mdio-mux-gpio", "mdio-mux"; 327 mdio-parent-bus = <&mdio0>; 328 gpios = <&gpio0 1 0>, <&gpio0 0 0>; 329 330 p4080mdio0: mdio@0 { 331 #address-cells = <1>; 332 #size-cells = <0>; 333 reg = <0>; 334 335 phyrgmii: ethernet-phy@0 { 336 reg = <0x0>; 337 }; 338 }; 339 340 p4080mdio1: mdio@1 { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <1>; 344 345 phy5: ethernet-phy@1c { 346 reg = <0x1c>; 347 }; 348 349 phy6: ethernet-phy@1d { 350 reg = <0x1d>; 351 }; 352 353 phy7: ethernet-phy@1e { 354 reg = <0x1e>; 355 }; 356 357 phy8: ethernet-phy@1f { 358 reg = <0x1f>; 359 }; 360 }; 361 362 p4080mdio2: mdio@2 { 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <2>; 366 status = "disabled"; 367 368 phy5slot3: ethernet-phy@1c { 369 reg = <0x1c>; 370 }; 371 372 phy6slot3: ethernet-phy@1d { 373 reg = <0x1d>; 374 }; 375 376 phy7slot3: ethernet-phy@1e { 377 reg = <0x1e>; 378 }; 379 380 phy8slot3: ethernet-phy@1f { 381 reg = <0x1f>; 382 }; 383 }; 384 385 p4080mdio3: mdio@3 { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <3>; 389 390 phy0: ethernet-phy@1c { 391 reg = <0x1c>; 392 }; 393 394 phy1: ethernet-phy@1d { 395 reg = <0x1d>; 396 }; 397 398 phy2: ethernet-phy@1e { 399 reg = <0x1e>; 400 }; 401 402 phy3: ethernet-phy@1f { 403 reg = <0x1f>; 404 }; 405 }; 406 }; 407 408 mdio-mux-emi2 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 compatible = "mdio-mux-gpio", "mdio-mux"; 412 mdio-parent-bus = <&xmdio0>; 413 gpios = <&gpio0 3 0>, <&gpio0 2 0>; 414 415 p4080xmdio1: mdio@1 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <1>; 419 420 phy11: ethernet-phy@0 { 421 compatible = "ethernet-phy-ieee802.3-c45"; 422 reg = <0x0>; 423 }; 424 }; 425 426 p4080xmdio3: mdio@3 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <3>; 430 431 phy10: ethernet-phy@4 { 432 compatible = "ethernet-phy-ieee802.3-c45"; 433 reg = <0x4>; 434 }; 435 }; 436 }; 437}; 438 439/include/ "p4080si-post.dtsi" 440