1/* 2 * MPC8568 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus"; 39 interrupts = <19 2 0 0>; 40 sleep = <&pmc 0x08000000>; 41}; 42 43/* controller at 0x8000 */ 44&pci0 { 45 compatible = "fsl,mpc8540-pci"; 46 device_type = "pci"; 47 interrupts = <24 0x2 0 0>; 48 bus-range = <0 0xff>; 49 #interrupt-cells = <1>; 50 #size-cells = <2>; 51 #address-cells = <3>; 52 sleep = <&pmc 0x80000000>; 53}; 54 55/* controller at 0xa000 */ 56&pci1 { 57 compatible = "fsl,mpc8548-pcie"; 58 device_type = "pci"; 59 #size-cells = <2>; 60 #address-cells = <3>; 61 bus-range = <0 255>; 62 clock-frequency = <33333333>; 63 interrupts = <26 2 0 0>; 64 sleep = <&pmc 0x20000000>; 65 66 pcie@0 { 67 reg = <0 0 0 0 0>; 68 #interrupt-cells = <1>; 69 #size-cells = <2>; 70 #address-cells = <3>; 71 device_type = "pci"; 72 interrupts = <26 2 0 0>; 73 interrupt-map-mask = <0xf800 0 0 7>; 74 interrupt-map = < 75 /* IDSEL 0x0 */ 76 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 77 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 78 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 79 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 80 >; 81 }; 82}; 83 84&rio { 85 #address-cells = <2>; 86 #size-cells = <2>; 87 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; 88 interrupts = <48 2 0 0 /* error */ 89 49 2 0 0 /* bell_outb */ 90 50 2 0 0 /* bell_inb */ 91 53 2 0 0 /* msg1_tx */ 92 54 2 0 0 /* msg1_rx */ 93 55 2 0 0 /* msg2_tx */ 94 56 2 0 0 /* msg2_rx */>; 95 sleep = <&pmc 0x00080000 /* controller */ 96 &pmc 0x00040000>; /* message unit */ 97}; 98 99&soc { 100 #address-cells = <1>; 101 #size-cells = <1>; 102 device_type = "soc"; 103 compatible = "fsl,mpc8568-immr", "simple-bus"; 104 bus-frequency = <0>; // Filled out by uboot. 105 106 ecm-law@0 { 107 compatible = "fsl,ecm-law"; 108 reg = <0x0 0x1000>; 109 fsl,num-laws = <10>; 110 }; 111 112 ecm@1000 { 113 compatible = "fsl,mpc8568-ecm", "fsl,ecm"; 114 reg = <0x1000 0x1000>; 115 interrupts = <17 2 0 0>; 116 }; 117 118 memory-controller@2000 { 119 compatible = "fsl,mpc8568-memory-controller"; 120 reg = <0x2000 0x1000>; 121 interrupts = <18 2 0 0>; 122 }; 123 124 i2c-sleep-nexus { 125 #address-cells = <1>; 126 #size-cells = <1>; 127 compatible = "simple-bus"; 128 sleep = <&pmc 0x00000004>; 129 ranges; 130 131/include/ "pq3-i2c-0.dtsi" 132/include/ "pq3-i2c-1.dtsi" 133 134 }; 135 136 duart-sleep-nexus { 137 #address-cells = <1>; 138 #size-cells = <1>; 139 compatible = "simple-bus"; 140 sleep = <&pmc 0x00000002>; 141 ranges; 142 143/include/ "pq3-duart-0.dtsi" 144 145 }; 146 147 L2: l2-cache-controller@20000 { 148 compatible = "fsl,mpc8568-l2-cache-controller"; 149 reg = <0x20000 0x1000>; 150 cache-line-size = <32>; // 32 bytes 151 cache-size = <0x80000>; // L2, 512K 152 interrupts = <16 2 0 0>; 153 }; 154 155/include/ "pq3-dma-0.dtsi" 156 dma@21300 { 157 sleep = <&pmc 0x00000400>; 158 }; 159 160/include/ "pq3-etsec1-0.dtsi" 161 ethernet@24000 { 162 sleep = <&pmc 0x00000080>; 163 }; 164 165/include/ "pq3-etsec1-1.dtsi" 166 ethernet@25000 { 167 sleep = <&pmc 0x00000040>; 168 }; 169 170 par_io@e0100 { 171 reg = <0xe0100 0x100>; 172 device_type = "par_io"; 173 }; 174 175/include/ "pq3-sec2.1-0.dtsi" 176 crypto@30000 { 177 sleep = <&pmc 0x01000000>; 178 }; 179 180/include/ "pq3-mpic.dtsi" 181 182 global-utilities@e0000 { 183 #address-cells = <1>; 184 #size-cells = <1>; 185 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts"; 186 reg = <0xe0000 0x1000>; 187 ranges = <0 0xe0000 0x1000>; 188 fsl,has-rstcr; 189 190 pmc: power@70 { 191 compatible = "fsl,mpc8568-pmc", 192 "fsl,mpc8548-pmc"; 193 reg = <0x70 0x20>; 194 }; 195 }; 196}; 197 198&qe { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 device_type = "qe"; 202 compatible = "fsl,qe"; 203 sleep = <&pmc 0x00000800>; 204 brg-frequency = <0>; 205 bus-frequency = <396000000>; 206 fsl,qe-num-riscs = <2>; 207 fsl,qe-num-snums = <28>; 208 209 qeic: interrupt-controller@80 { 210 interrupt-controller; 211 compatible = "fsl,qe-ic"; 212 #address-cells = <0>; 213 #interrupt-cells = <1>; 214 reg = <0x80 0x80>; 215 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30 216 interrupt-parent = <&mpic>; 217 }; 218 219 spi@4c0 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "fsl,spi"; 223 reg = <0x4c0 0x40>; 224 cell-index = <0>; 225 interrupts = <2>; 226 interrupt-parent = <&qeic>; 227 }; 228 229 spi@500 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 cell-index = <1>; 233 compatible = "fsl,spi"; 234 reg = <0x500 0x40>; 235 interrupts = <1>; 236 interrupt-parent = <&qeic>; 237 }; 238 239 ucc@2000 { 240 cell-index = <1>; 241 reg = <0x2000 0x200>; 242 interrupts = <32>; 243 interrupt-parent = <&qeic>; 244 }; 245 246 ucc@3000 { 247 cell-index = <2>; 248 reg = <0x3000 0x200>; 249 interrupts = <33>; 250 interrupt-parent = <&qeic>; 251 }; 252 253 muram@10000 { 254 #address-cells = <1>; 255 #size-cells = <1>; 256 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 257 ranges = <0x0 0x10000 0x10000>; 258 259 data-only@0 { 260 compatible = "fsl,qe-muram-data", 261 "fsl,cpm-muram-data"; 262 reg = <0x0 0x10000>; 263 }; 264 }; 265}; 266