xref: /linux/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi (revision b43ab901d671e3e3cad425ea5e9a3c74e266dcdd)
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36	#address-cells = <2>;
37	#size-cells = <1>;
38	compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
39	interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
45	device_type = "pci";
46	interrupts = <24 0x2 0 0>;
47	bus-range = <0 0xff>;
48	#interrupt-cells = <1>;
49	#size-cells = <2>;
50	#address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55	compatible = "fsl,mpc8540-pci";
56	device_type = "pci";
57	interrupts = <25 0x2 0 0>;
58	bus-range = <0 0xff>;
59	#interrupt-cells = <1>;
60	#size-cells = <2>;
61	#address-cells = <3>;
62};
63
64/* controller at 0xa000 */
65&pci2 {
66	compatible = "fsl,mpc8548-pcie";
67	device_type = "pci";
68	#size-cells = <2>;
69	#address-cells = <3>;
70	bus-range = <0 255>;
71	clock-frequency = <33333333>;
72	interrupts = <26 2 0 0>;
73
74	pcie@0 {
75		reg = <0 0 0 0 0>;
76		#interrupt-cells = <1>;
77		#size-cells = <2>;
78		#address-cells = <3>;
79		device_type = "pci";
80		interrupts = <26 2 0 0>;
81		interrupt-map-mask = <0xf800 0 0 7>;
82		interrupt-map = <
83			/* IDSEL 0x0 */
84			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
85			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
86			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
87			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
88			>;
89	};
90};
91
92&soc {
93	#address-cells = <1>;
94	#size-cells = <1>;
95	device_type = "soc";
96	compatible = "fsl,mpc8548-immr", "simple-bus";
97	bus-frequency = <0>;		// Filled out by uboot.
98
99	ecm-law@0 {
100		compatible = "fsl,ecm-law";
101		reg = <0x0 0x1000>;
102		fsl,num-laws = <10>;
103	};
104
105	ecm@1000 {
106		compatible = "fsl,mpc8548-ecm", "fsl,ecm";
107		reg = <0x1000 0x1000>;
108		interrupts = <17 2 0 0>;
109	};
110
111	memory-controller@2000 {
112		compatible = "fsl,mpc8548-memory-controller";
113		reg = <0x2000 0x1000>;
114		interrupts = <18 2 0 0>;
115	};
116
117/include/ "pq3-i2c-0.dtsi"
118/include/ "pq3-i2c-1.dtsi"
119/include/ "pq3-duart-0.dtsi"
120
121	L2: l2-cache-controller@20000 {
122		compatible = "fsl,mpc8548-l2-cache-controller";
123		reg = <0x20000 0x1000>;
124		cache-line-size = <32>;	// 32 bytes
125		cache-size = <0x80000>; // L2, 512K
126		interrupts = <16 2 0 0>;
127	};
128
129/include/ "pq3-dma-0.dtsi"
130/include/ "pq3-etsec1-0.dtsi"
131/include/ "pq3-etsec1-1.dtsi"
132/include/ "pq3-etsec1-2.dtsi"
133/include/ "pq3-etsec1-3.dtsi"
134
135/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi"
137
138	global-utilities@e0000 {
139		compatible = "fsl,mpc8548-guts";
140		reg = <0xe0000 0x1000>;
141		fsl,has-rstcr;
142	};
143};
144