xref: /linux/arch/powerpc/boot/dts/fsl/mpc8544ds.dtsi (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1/*
2 * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36	nor@0,0 {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "cfi-flash";
40		reg = <0x0 0x0 0x800000>;
41		bank-width = <2>;
42		device-width = <1>;
43
44		partition@0 {
45			reg = <0x0 0x10000>;
46			label = "dtb-nor";
47		};
48
49		partition@20000 {
50			reg = <0x20000 0x30000>;
51			label = "diagnostic-nor";
52			read-only;
53		};
54
55		partition@200000 {
56			reg = <0x200000 0x200000>;
57			label = "dink-nor";
58			read-only;
59		};
60
61		partition@400000 {
62			reg = <0x400000 0x380000>;
63			label = "kernel-nor";
64		};
65
66		partition@780000 {
67			reg = <0x780000 0x80000>;
68			label = "u-boot-nor";
69			read-only;
70		};
71	};
72};
73
74&board_soc {
75	enet0: ethernet@24000 {
76		phy-handle = <&phy0>;
77		tbi-handle = <&tbi0>;
78		phy-connection-type = "rgmii-id";
79	};
80
81	mdio@24520 {
82		phy0: ethernet-phy@0 {
83			interrupts = <10 1 0 0>;
84			reg = <0x0>;
85		};
86		phy1: ethernet-phy@1 {
87			interrupts = <10 1 0 0>;
88			reg = <0x1>;
89		};
90
91		sgmii_phy0: sgmii-phy@0 {
92			interrupts = <6 1 0 0>;
93			reg = <0x1c>;
94		};
95		sgmii_phy1: sgmii-phy@1 {
96			interrupts = <6 1 0 0>;
97			reg = <0x1d>;
98		};
99
100		tbi0: tbi-phy@11 {
101			reg = <0x11>;
102			device_type = "tbi-phy";
103		};
104	};
105
106	enet2: ethernet@26000 {
107		phy-handle = <&phy1>;
108		tbi-handle = <&tbi1>;
109		phy-connection-type = "rgmii-id";
110	};
111
112	mdio@26520 {
113		tbi1: tbi-phy@11 {
114			reg = <0x11>;
115			device_type = "tbi-phy";
116		};
117	};
118};
119
120&board_pci3 {
121	pcie@0 {
122		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
123		interrupt-map = <
124			// IDSEL 0x1c  USB
125			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
126			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
127			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
128			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
129
130			// IDSEL 0x1d  Audio
131			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
132
133			// IDSEL 0x1e Legacy
134			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
135			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
136
137			// IDSEL 0x1f IDE/SATA
138			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
139			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
140			>;
141
142
143		uli1575@0 {
144			reg = <0x0 0x0 0x0 0x0 0x0>;
145			#size-cells = <2>;
146			#address-cells = <3>;
147			ranges = <0x2000000 0x0 0xb0000000
148				  0x2000000 0x0 0xb0000000
149				  0x0 0x100000
150
151				  0x1000000 0x0 0x0
152				  0x1000000 0x0 0x0
153				  0x0 0x100000>;
154			isa@1e {
155				device_type = "isa";
156				#interrupt-cells = <2>;
157				#size-cells = <1>;
158				#address-cells = <2>;
159				reg = <0xf000 0x0 0x0 0x0 0x0>;
160				ranges = <0x1 0x0 0x1000000 0x0 0x0
161					  0x1000>;
162				interrupt-parent = <&i8259>;
163
164				i8259: interrupt-controller@20 {
165					reg = <0x1 0x20 0x2
166					       0x1 0xa0 0x2
167					       0x1 0x4d0 0x2>;
168					interrupt-controller;
169					device_type = "interrupt-controller";
170					#address-cells = <0>;
171					#interrupt-cells = <2>;
172					compatible = "chrp,iic";
173					interrupts = <9 2 0 0>;
174					interrupt-parent = <&mpic>;
175				};
176
177				i8042@60 {
178					#size-cells = <0>;
179					#address-cells = <1>;
180					reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
181					interrupts = <1 3 12 3>;
182					interrupt-parent =
183						<&i8259>;
184
185					keyboard@0 {
186						reg = <0x0>;
187						compatible = "pnpPNP,303";
188					};
189
190					mouse@1 {
191						reg = <0x1>;
192						compatible = "pnpPNP,f03";
193					};
194				};
195
196				rtc@70 {
197					compatible = "pnpPNP,b00";
198					reg = <0x1 0x70 0x2>;
199				};
200
201				gpio@400 {
202					reg = <0x1 0x400 0x80>;
203				};
204			};
205		};
206	};
207};
208