xref: /linux/arch/powerpc/boot/dts/fsl/kmcent2.dts (revision fdc8c4adb6a465b5873df97fcbd1cb332ade019b)
1*fdc8c4adSValentin Longchamp/*
2*fdc8c4adSValentin Longchamp * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
3*fdc8c4adSValentin Longchamp *
4*fdc8c4adSValentin Longchamp * (C) Copyright 2016
5*fdc8c4adSValentin Longchamp * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
6*fdc8c4adSValentin Longchamp *
7*fdc8c4adSValentin Longchamp * Copyright 2014 - 2015 Freescale Semiconductor Inc.
8*fdc8c4adSValentin Longchamp *
9*fdc8c4adSValentin Longchamp * This program is free software; you can redistribute  it and/or modify it
10*fdc8c4adSValentin Longchamp * under  the terms of  the GNU General  Public License as published by the
11*fdc8c4adSValentin Longchamp * Free Software Foundation;  either version 2 of the  License, or (at your
12*fdc8c4adSValentin Longchamp * option) any later version.
13*fdc8c4adSValentin Longchamp */
14*fdc8c4adSValentin Longchamp
15*fdc8c4adSValentin Longchamp/include/ "t104xsi-pre.dtsi"
16*fdc8c4adSValentin Longchamp
17*fdc8c4adSValentin Longchamp/ {
18*fdc8c4adSValentin Longchamp	model = "keymile,kmcent2";
19*fdc8c4adSValentin Longchamp	compatible = "keymile,kmcent2";
20*fdc8c4adSValentin Longchamp
21*fdc8c4adSValentin Longchamp	aliases {
22*fdc8c4adSValentin Longchamp		front_phy = &front_phy;
23*fdc8c4adSValentin Longchamp	};
24*fdc8c4adSValentin Longchamp
25*fdc8c4adSValentin Longchamp	reserved-memory {
26*fdc8c4adSValentin Longchamp		#address-cells = <2>;
27*fdc8c4adSValentin Longchamp		#size-cells = <2>;
28*fdc8c4adSValentin Longchamp		ranges;
29*fdc8c4adSValentin Longchamp
30*fdc8c4adSValentin Longchamp		bman_fbpr: bman-fbpr {
31*fdc8c4adSValentin Longchamp			size = <0 0x1000000>;
32*fdc8c4adSValentin Longchamp			alignment = <0 0x1000000>;
33*fdc8c4adSValentin Longchamp		};
34*fdc8c4adSValentin Longchamp		qman_fqd: qman-fqd {
35*fdc8c4adSValentin Longchamp			size = <0 0x400000>;
36*fdc8c4adSValentin Longchamp			alignment = <0 0x400000>;
37*fdc8c4adSValentin Longchamp		};
38*fdc8c4adSValentin Longchamp		qman_pfdr: qman-pfdr {
39*fdc8c4adSValentin Longchamp			size = <0 0x2000000>;
40*fdc8c4adSValentin Longchamp			alignment = <0 0x2000000>;
41*fdc8c4adSValentin Longchamp		};
42*fdc8c4adSValentin Longchamp	};
43*fdc8c4adSValentin Longchamp
44*fdc8c4adSValentin Longchamp	ifc: localbus@ffe124000 {
45*fdc8c4adSValentin Longchamp		reg = <0xf 0xfe124000 0 0x2000>;
46*fdc8c4adSValentin Longchamp		ranges = <0 0 0xf 0xe8000000 0x04000000
47*fdc8c4adSValentin Longchamp			  1 0 0xf 0xfa000000 0x00010000
48*fdc8c4adSValentin Longchamp			  2 0 0xf 0xfb000000 0x00010000
49*fdc8c4adSValentin Longchamp			  4 0 0xf 0xc0000000 0x08000000
50*fdc8c4adSValentin Longchamp			  6 0 0xf 0xd0000000 0x08000000
51*fdc8c4adSValentin Longchamp			  7 0 0xf 0xd8000000 0x08000000>;
52*fdc8c4adSValentin Longchamp
53*fdc8c4adSValentin Longchamp		nor@0,0 {
54*fdc8c4adSValentin Longchamp			#address-cells = <1>;
55*fdc8c4adSValentin Longchamp			#size-cells = <1>;
56*fdc8c4adSValentin Longchamp			compatible = "cfi-flash";
57*fdc8c4adSValentin Longchamp			reg = <0x0 0x0 0x04000000>;
58*fdc8c4adSValentin Longchamp			bank-width = <2>;
59*fdc8c4adSValentin Longchamp			device-width = <2>;
60*fdc8c4adSValentin Longchamp		};
61*fdc8c4adSValentin Longchamp
62*fdc8c4adSValentin Longchamp		nand@1,0 {
63*fdc8c4adSValentin Longchamp			#address-cells = <1>;
64*fdc8c4adSValentin Longchamp			#size-cells = <1>;
65*fdc8c4adSValentin Longchamp			compatible = "fsl,ifc-nand";
66*fdc8c4adSValentin Longchamp			reg = <0x1 0x0 0x10000>;
67*fdc8c4adSValentin Longchamp		};
68*fdc8c4adSValentin Longchamp
69*fdc8c4adSValentin Longchamp		board-control@2,0 {
70*fdc8c4adSValentin Longchamp			compatible = "keymile,qriox";
71*fdc8c4adSValentin Longchamp			reg = <0x2 0x0 0x80>;
72*fdc8c4adSValentin Longchamp		};
73*fdc8c4adSValentin Longchamp
74*fdc8c4adSValentin Longchamp		chassis-mgmt@6,0 {
75*fdc8c4adSValentin Longchamp			compatible = "keymile,bfticu";
76*fdc8c4adSValentin Longchamp			reg = <6 0 0x100>;
77*fdc8c4adSValentin Longchamp			interrupt-controller;
78*fdc8c4adSValentin Longchamp			interrupt-parent = <&mpic>;
79*fdc8c4adSValentin Longchamp			interrupts = <11 1 0 0>;
80*fdc8c4adSValentin Longchamp			#interrupt-cells = <1>;
81*fdc8c4adSValentin Longchamp		};
82*fdc8c4adSValentin Longchamp
83*fdc8c4adSValentin Longchamp	};
84*fdc8c4adSValentin Longchamp
85*fdc8c4adSValentin Longchamp	memory {
86*fdc8c4adSValentin Longchamp		device_type = "memory";
87*fdc8c4adSValentin Longchamp	};
88*fdc8c4adSValentin Longchamp
89*fdc8c4adSValentin Longchamp	dcsr: dcsr@f00000000 {
90*fdc8c4adSValentin Longchamp		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
91*fdc8c4adSValentin Longchamp	};
92*fdc8c4adSValentin Longchamp
93*fdc8c4adSValentin Longchamp	bportals: bman-portals@ff4000000 {
94*fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xf4000000 0x2000000>;
95*fdc8c4adSValentin Longchamp	};
96*fdc8c4adSValentin Longchamp
97*fdc8c4adSValentin Longchamp	qportals: qman-portals@ff6000000 {
98*fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xf6000000 0x2000000>;
99*fdc8c4adSValentin Longchamp	};
100*fdc8c4adSValentin Longchamp
101*fdc8c4adSValentin Longchamp	soc: soc@ffe000000 {
102*fdc8c4adSValentin Longchamp		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
103*fdc8c4adSValentin Longchamp		reg = <0xf 0xfe000000 0 0x00001000>;
104*fdc8c4adSValentin Longchamp
105*fdc8c4adSValentin Longchamp		spi@110000 {
106*fdc8c4adSValentin Longchamp			network-clock@1 {
107*fdc8c4adSValentin Longchamp				compatible = "zarlink,zl30364";
108*fdc8c4adSValentin Longchamp				reg = <1>;
109*fdc8c4adSValentin Longchamp				spi-max-frequency = <1000000>;
110*fdc8c4adSValentin Longchamp			};
111*fdc8c4adSValentin Longchamp		};
112*fdc8c4adSValentin Longchamp
113*fdc8c4adSValentin Longchamp		sdhc@114000 {
114*fdc8c4adSValentin Longchamp			status = "disabled";
115*fdc8c4adSValentin Longchamp		};
116*fdc8c4adSValentin Longchamp
117*fdc8c4adSValentin Longchamp		i2c@118000 {
118*fdc8c4adSValentin Longchamp			clock-frequency = <100000>;
119*fdc8c4adSValentin Longchamp
120*fdc8c4adSValentin Longchamp			mux@70 {
121*fdc8c4adSValentin Longchamp				compatible = "nxp,pca9547";
122*fdc8c4adSValentin Longchamp				reg = <0x70>;
123*fdc8c4adSValentin Longchamp				#address-cells = <1>;
124*fdc8c4adSValentin Longchamp				#size-cells = <0>;
125*fdc8c4adSValentin Longchamp				i2c-mux-idle-disconnect;
126*fdc8c4adSValentin Longchamp
127*fdc8c4adSValentin Longchamp				i2c@0 {
128*fdc8c4adSValentin Longchamp					reg = <0>;
129*fdc8c4adSValentin Longchamp					#address-cells = <1>;
130*fdc8c4adSValentin Longchamp					#size-cells = <0>;
131*fdc8c4adSValentin Longchamp
132*fdc8c4adSValentin Longchamp					eeprom@54 {
133*fdc8c4adSValentin Longchamp						compatible = "24c02";
134*fdc8c4adSValentin Longchamp						reg = <0x54>;
135*fdc8c4adSValentin Longchamp						pagesize = <2>;
136*fdc8c4adSValentin Longchamp						read-only;
137*fdc8c4adSValentin Longchamp						label = "ddr3-spd";
138*fdc8c4adSValentin Longchamp					};
139*fdc8c4adSValentin Longchamp				};
140*fdc8c4adSValentin Longchamp
141*fdc8c4adSValentin Longchamp				i2c@7 {
142*fdc8c4adSValentin Longchamp					reg = <7>;
143*fdc8c4adSValentin Longchamp					#address-cells = <1>;
144*fdc8c4adSValentin Longchamp					#size-cells = <0>;
145*fdc8c4adSValentin Longchamp
146*fdc8c4adSValentin Longchamp					temp-sensor@48 {
147*fdc8c4adSValentin Longchamp						compatible = "national,lm75";
148*fdc8c4adSValentin Longchamp						reg = <0x48>;
149*fdc8c4adSValentin Longchamp						label = "SENSOR_0";
150*fdc8c4adSValentin Longchamp					};
151*fdc8c4adSValentin Longchamp					temp-sensor@4a {
152*fdc8c4adSValentin Longchamp						compatible = "national,lm75";
153*fdc8c4adSValentin Longchamp						reg = <0x4a>;
154*fdc8c4adSValentin Longchamp						label = "SENSOR_2";
155*fdc8c4adSValentin Longchamp					};
156*fdc8c4adSValentin Longchamp					temp-sensor@4b {
157*fdc8c4adSValentin Longchamp						compatible = "national,lm75";
158*fdc8c4adSValentin Longchamp						reg = <0x4b>;
159*fdc8c4adSValentin Longchamp						label = "SENSOR_3";
160*fdc8c4adSValentin Longchamp					};
161*fdc8c4adSValentin Longchamp				};
162*fdc8c4adSValentin Longchamp			};
163*fdc8c4adSValentin Longchamp		};
164*fdc8c4adSValentin Longchamp
165*fdc8c4adSValentin Longchamp		i2c@118100 {
166*fdc8c4adSValentin Longchamp			clock-frequency = <100000>;
167*fdc8c4adSValentin Longchamp
168*fdc8c4adSValentin Longchamp			eeprom@50 {
169*fdc8c4adSValentin Longchamp				compatible = "atmel,24c08";
170*fdc8c4adSValentin Longchamp				reg = <0x50>;
171*fdc8c4adSValentin Longchamp				pagesize = <16>;
172*fdc8c4adSValentin Longchamp			};
173*fdc8c4adSValentin Longchamp
174*fdc8c4adSValentin Longchamp			eeprom@54 {
175*fdc8c4adSValentin Longchamp				compatible = "atmel,24c08";
176*fdc8c4adSValentin Longchamp				reg = <0x54>;
177*fdc8c4adSValentin Longchamp				pagesize = <16>;
178*fdc8c4adSValentin Longchamp			};
179*fdc8c4adSValentin Longchamp		};
180*fdc8c4adSValentin Longchamp
181*fdc8c4adSValentin Longchamp		i2c@119000 {
182*fdc8c4adSValentin Longchamp			status = "disabled";
183*fdc8c4adSValentin Longchamp		};
184*fdc8c4adSValentin Longchamp
185*fdc8c4adSValentin Longchamp		i2c@119100 {
186*fdc8c4adSValentin Longchamp			status = "disabled";
187*fdc8c4adSValentin Longchamp		};
188*fdc8c4adSValentin Longchamp
189*fdc8c4adSValentin Longchamp		serial2: serial@11d500 {
190*fdc8c4adSValentin Longchamp			status = "disabled";
191*fdc8c4adSValentin Longchamp		};
192*fdc8c4adSValentin Longchamp
193*fdc8c4adSValentin Longchamp		serial3: serial@11d600 {
194*fdc8c4adSValentin Longchamp			status = "disabled";
195*fdc8c4adSValentin Longchamp		};
196*fdc8c4adSValentin Longchamp
197*fdc8c4adSValentin Longchamp		usb0: usb@210000 {
198*fdc8c4adSValentin Longchamp			status = "disabled";
199*fdc8c4adSValentin Longchamp		};
200*fdc8c4adSValentin Longchamp		usb1: usb@211000 {
201*fdc8c4adSValentin Longchamp			status = "disabled";
202*fdc8c4adSValentin Longchamp		};
203*fdc8c4adSValentin Longchamp
204*fdc8c4adSValentin Longchamp		display@180000 {
205*fdc8c4adSValentin Longchamp			status = "disabled";
206*fdc8c4adSValentin Longchamp		};
207*fdc8c4adSValentin Longchamp
208*fdc8c4adSValentin Longchamp		sata@220000 {
209*fdc8c4adSValentin Longchamp			status = "disabled";
210*fdc8c4adSValentin Longchamp		};
211*fdc8c4adSValentin Longchamp		sata@221000 {
212*fdc8c4adSValentin Longchamp			status = "disabled";
213*fdc8c4adSValentin Longchamp		};
214*fdc8c4adSValentin Longchamp
215*fdc8c4adSValentin Longchamp		fman@400000 {
216*fdc8c4adSValentin Longchamp			ethernet@e0000 {
217*fdc8c4adSValentin Longchamp				fixed-link = <0 1 1000 0 0>;
218*fdc8c4adSValentin Longchamp				phy-connection-type = "sgmii";
219*fdc8c4adSValentin Longchamp			};
220*fdc8c4adSValentin Longchamp
221*fdc8c4adSValentin Longchamp			ethernet@e2000 {
222*fdc8c4adSValentin Longchamp				fixed-link = <1 1 1000 0 0>;
223*fdc8c4adSValentin Longchamp				phy-connection-type = "sgmii";
224*fdc8c4adSValentin Longchamp			};
225*fdc8c4adSValentin Longchamp
226*fdc8c4adSValentin Longchamp			ethernet@e4000 {
227*fdc8c4adSValentin Longchamp				status = "disabled";
228*fdc8c4adSValentin Longchamp			};
229*fdc8c4adSValentin Longchamp
230*fdc8c4adSValentin Longchamp			ethernet@e6000 {
231*fdc8c4adSValentin Longchamp				status = "disabled";
232*fdc8c4adSValentin Longchamp			};
233*fdc8c4adSValentin Longchamp
234*fdc8c4adSValentin Longchamp			ethernet@e8000 {
235*fdc8c4adSValentin Longchamp				phy-handle = <&front_phy>;
236*fdc8c4adSValentin Longchamp				phy-connection-type = "rgmii";
237*fdc8c4adSValentin Longchamp			};
238*fdc8c4adSValentin Longchamp
239*fdc8c4adSValentin Longchamp			mdio0: mdio@fc000 {
240*fdc8c4adSValentin Longchamp				front_phy: ethernet-phy@11 {
241*fdc8c4adSValentin Longchamp					reg = <0x11>;
242*fdc8c4adSValentin Longchamp				};
243*fdc8c4adSValentin Longchamp			};
244*fdc8c4adSValentin Longchamp		};
245*fdc8c4adSValentin Longchamp	};
246*fdc8c4adSValentin Longchamp
247*fdc8c4adSValentin Longchamp
248*fdc8c4adSValentin Longchamp	pci0: pcie@ffe240000 {
249*fdc8c4adSValentin Longchamp		reg = <0xf 0xfe240000 0 0x10000>;
250*fdc8c4adSValentin Longchamp		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
251*fdc8c4adSValentin Longchamp			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
252*fdc8c4adSValentin Longchamp		pcie@0 {
253*fdc8c4adSValentin Longchamp			ranges = <0x02000000 0 0xe0000000
254*fdc8c4adSValentin Longchamp				  0x02000000 0 0xe0000000
255*fdc8c4adSValentin Longchamp				  0 0x20000000
256*fdc8c4adSValentin Longchamp
257*fdc8c4adSValentin Longchamp				  0x01000000 0 0x00000000
258*fdc8c4adSValentin Longchamp				  0x01000000 0 0x00000000
259*fdc8c4adSValentin Longchamp				  0 0x00010000>;
260*fdc8c4adSValentin Longchamp		};
261*fdc8c4adSValentin Longchamp	};
262*fdc8c4adSValentin Longchamp
263*fdc8c4adSValentin Longchamp	pci1: pcie@ffe250000 {
264*fdc8c4adSValentin Longchamp		status = "disabled";
265*fdc8c4adSValentin Longchamp	};
266*fdc8c4adSValentin Longchamp
267*fdc8c4adSValentin Longchamp	pci2: pcie@ffe260000 {
268*fdc8c4adSValentin Longchamp		status = "disabled";
269*fdc8c4adSValentin Longchamp	};
270*fdc8c4adSValentin Longchamp
271*fdc8c4adSValentin Longchamp	pci3: pcie@ffe270000 {
272*fdc8c4adSValentin Longchamp		status = "disabled";
273*fdc8c4adSValentin Longchamp	};
274*fdc8c4adSValentin Longchamp
275*fdc8c4adSValentin Longchamp	qe: qe@ffe140000 {
276*fdc8c4adSValentin Longchamp		ranges = <0x0 0xf 0xfe140000 0x40000>;
277*fdc8c4adSValentin Longchamp		reg = <0xf 0xfe140000 0 0x480>;
278*fdc8c4adSValentin Longchamp		brg-frequency = <0>;
279*fdc8c4adSValentin Longchamp		bus-frequency = <0>;
280*fdc8c4adSValentin Longchamp
281*fdc8c4adSValentin Longchamp		si1: si@700 {
282*fdc8c4adSValentin Longchamp			compatible = "fsl,t1040-qe-si";
283*fdc8c4adSValentin Longchamp			reg = <0x700 0x80>;
284*fdc8c4adSValentin Longchamp		};
285*fdc8c4adSValentin Longchamp
286*fdc8c4adSValentin Longchamp		siram1: siram@1000 {
287*fdc8c4adSValentin Longchamp			compatible = "fsl,t1040-qe-siram";
288*fdc8c4adSValentin Longchamp			reg = <0x1000 0x800>;
289*fdc8c4adSValentin Longchamp		};
290*fdc8c4adSValentin Longchamp
291*fdc8c4adSValentin Longchamp		ucc_hdlc: ucc@2000 {
292*fdc8c4adSValentin Longchamp			device_type = "hdlc";
293*fdc8c4adSValentin Longchamp			compatible = "fsl,ucc-hdlc";
294*fdc8c4adSValentin Longchamp			rx-clock-name = "clk9";
295*fdc8c4adSValentin Longchamp			tx-clock-name = "clk9";
296*fdc8c4adSValentin Longchamp			fsl,tx-timeslot-mask = <0xfffffffe>;
297*fdc8c4adSValentin Longchamp			fsl,rx-timeslot-mask = <0xfffffffe>;
298*fdc8c4adSValentin Longchamp			fsl,siram-entry-id = <0>;
299*fdc8c4adSValentin Longchamp		};
300*fdc8c4adSValentin Longchamp	};
301*fdc8c4adSValentin Longchamp};
302*fdc8c4adSValentin Longchamp
303*fdc8c4adSValentin Longchamp#include "t1040si-post.dtsi"
304