xref: /linux/arch/powerpc/boot/dts/fsl/cyrus_p5020.dts (revision e65e175b07bef5974045cc42238de99057669ca7) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cyrus 5020 Device Tree Source, based on p5020ds.dts
4 *
5 * Copyright 2015 Andy Fleming
6 *
7 * p5020ds.dts copyright:
8 * Copyright 2010 - 2014 Freescale Semiconductor Inc.
9 */
10
11/include/ "p5020si-pre.dtsi"
12
13/ {
14	model = "varisys,CYRUS";
15	compatible = "varisys,CYRUS";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&mpic>;
19
20	memory {
21		device_type = "memory";
22	};
23
24	reserved-memory {
25		#address-cells = <2>;
26		#size-cells = <2>;
27		ranges;
28
29		bman_fbpr: bman-fbpr {
30			size = <0 0x1000000>;
31			alignment = <0 0x1000000>;
32		};
33		qman_fqd: qman-fqd {
34			size = <0 0x400000>;
35			alignment = <0 0x400000>;
36		};
37		qman_pfdr: qman-pfdr {
38			size = <0 0x2000000>;
39			alignment = <0 0x2000000>;
40		};
41	};
42
43	dcsr: dcsr@f00000000 {
44		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
45	};
46
47	bportals: bman-portals@ff4000000 {
48		ranges = <0x0 0xf 0xf4000000 0x200000>;
49	};
50
51	qportals: qman-portals@ff4200000 {
52		ranges = <0x0 0xf 0xf4200000 0x200000>;
53	};
54
55	soc: soc@ffe000000 {
56		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57		reg = <0xf 0xfe000000 0 0x00001000>;
58		spi@110000 {
59		};
60
61		i2c@118100 {
62		};
63
64		i2c@119100 {
65			rtc@6f {
66				compatible = "microchip,mcp7941x";
67				reg = <0x6f>;
68			};
69		};
70	};
71
72	rio: rapidio@ffe0c0000 {
73		reg = <0xf 0xfe0c0000 0 0x11000>;
74
75		port1 {
76			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
77		};
78		port2 {
79			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
80		};
81	};
82
83	lbc: localbus@ffe124000 {
84		reg = <0xf 0xfe124000 0 0x1000>;
85		ranges = <0 0 0xf 0xe8000000 0x08000000
86			  2 0 0xf 0xffa00000 0x00040000
87			  3 0 0xf 0xffdf0000 0x00008000>;
88	};
89
90	pci0: pcie@ffe200000 {
91		reg = <0xf 0xfe200000 0 0x1000>;
92		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
93			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
94		pcie@0 {
95			ranges = <0x02000000 0 0xe0000000
96				  0x02000000 0 0xe0000000
97				  0 0x20000000
98
99				  0x01000000 0 0x00000000
100				  0x01000000 0 0x00000000
101				  0 0x00010000>;
102		};
103	};
104
105	pci1: pcie@ffe201000 {
106		reg = <0xf 0xfe201000 0 0x1000>;
107		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
108			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
109		pcie@0 {
110			ranges = <0x02000000 0 0xe0000000
111				  0x02000000 0 0xe0000000
112				  0 0x20000000
113
114				  0x01000000 0 0x00000000
115				  0x01000000 0 0x00000000
116				  0 0x00010000>;
117		};
118	};
119
120	pci2: pcie@ffe202000 {
121		reg = <0xf 0xfe202000 0 0x1000>;
122		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
123			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
124		pcie@0 {
125			ranges = <0x02000000 0 0xe0000000
126				  0x02000000 0 0xe0000000
127				  0 0x20000000
128
129				  0x01000000 0 0x00000000
130				  0x01000000 0 0x00000000
131				  0 0x00010000>;
132		};
133	};
134
135	pci3: pcie@ffe203000 {
136		reg = <0xf 0xfe203000 0 0x1000>;
137		ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
138			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
139		pcie@0 {
140			ranges = <0x02000000 0 0xe0000000
141				  0x02000000 0 0xe0000000
142				  0 0x20000000
143
144				  0x01000000 0 0x00000000
145				  0x01000000 0 0x00000000
146				  0 0x00010000>;
147		};
148	};
149};
150
151/include/ "p5020si-post.dtsi"
152