1/* 2 * B4420 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2012 - 2014 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of 32 * this software, even if advised of the possibility of such damage. 33 */ 34 35&bman_fbpr { 36 compatible = "fsl,bman-fbpr"; 37 alloc-ranges = <0 0 0x10000 0>; 38}; 39 40&qman_fqd { 41 compatible = "fsl,qman-fqd"; 42 alloc-ranges = <0 0 0x10000 0>; 43}; 44 45&qman_pfdr { 46 compatible = "fsl,qman-pfdr"; 47 alloc-ranges = <0 0 0x10000 0>; 48}; 49 50&ifc { 51 #address-cells = <2>; 52 #size-cells = <1>; 53 compatible = "fsl,ifc", "simple-bus"; 54 interrupts = <25 2 0 0>; 55}; 56 57/* controller at 0x200000 */ 58&pci0 { 59 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4"; 60 device_type = "pci"; 61 #size-cells = <2>; 62 #address-cells = <3>; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 fsl,iommu-parent = <&pamu0>; 66 pcie@0 { 67 #interrupt-cells = <1>; 68 #size-cells = <2>; 69 #address-cells = <3>; 70 device_type = "pci"; 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; 73 interrupt-map-mask = <0xf800 0 0 7>; 74 interrupt-map = < 75 /* IDSEL 0x0 */ 76 0000 0 0 1 &mpic 40 1 0 0 77 0000 0 0 2 &mpic 1 1 0 0 78 0000 0 0 3 &mpic 2 1 0 0 79 0000 0 0 4 &mpic 3 1 0 0 80 >; 81 }; 82}; 83 84&dcsr { 85 #address-cells = <1>; 86 #size-cells = <1>; 87 compatible = "fsl,dcsr", "simple-bus"; 88 89 dcsr-epu@0 { 90 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu"; 91 interrupts = <52 2 0 0 92 84 2 0 0 93 85 2 0 0 94 94 2 0 0 95 95 2 0 0>; 96 reg = <0x0 0x1000>; 97 }; 98 dcsr-npc { 99 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc"; 100 reg = <0x1000 0x1000 0x1002000 0x10000>; 101 }; 102 dcsr-nxc@2000 { 103 compatible = "fsl,dcsr-nxc"; 104 reg = <0x2000 0x1000>; 105 }; 106 dcsr-corenet { 107 compatible = "fsl,dcsr-corenet"; 108 reg = <0x8000 0x1000 0x1A000 0x1000>; 109 }; 110 dcsr-dpaa@9000 { 111 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa"; 112 reg = <0x9000 0x1000>; 113 }; 114 dcsr-ocn@11000 { 115 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn"; 116 reg = <0x11000 0x1000>; 117 }; 118 dcsr-ddr@12000 { 119 compatible = "fsl,dcsr-ddr"; 120 dev-handle = <&ddr1>; 121 reg = <0x12000 0x1000>; 122 }; 123 dcsr-nal@18000 { 124 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal"; 125 reg = <0x18000 0x1000>; 126 }; 127 dcsr-rcpm@22000 { 128 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm"; 129 reg = <0x22000 0x1000>; 130 }; 131 dcsr-snpc@30000 { 132 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; 133 reg = <0x30000 0x1000 0x1022000 0x10000>; 134 }; 135 dcsr-snpc@31000 { 136 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc"; 137 reg = <0x31000 0x1000 0x1042000 0x10000>; 138 }; 139 dcsr-cpu-sb-proxy@100000 { 140 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 141 cpu-handle = <&cpu0>; 142 reg = <0x100000 0x1000 0x101000 0x1000>; 143 }; 144}; 145 146&bportals { 147 #address-cells = <0x1>; 148 #size-cells = <0x1>; 149 compatible = "simple-bus"; 150 151 bman-portal@0 { 152 compatible = "fsl,bman-portal"; 153 reg = <0x0 0x4000>, <0x1000000 0x1000>; 154 interrupts = <105 2 0 0>; 155 }; 156 bman-portal@4000 { 157 compatible = "fsl,bman-portal"; 158 reg = <0x4000 0x4000>, <0x1001000 0x1000>; 159 interrupts = <107 2 0 0>; 160 }; 161 bman-portal@8000 { 162 compatible = "fsl,bman-portal"; 163 reg = <0x8000 0x4000>, <0x1002000 0x1000>; 164 interrupts = <109 2 0 0>; 165 }; 166 bman-portal@c000 { 167 compatible = "fsl,bman-portal"; 168 reg = <0xc000 0x4000>, <0x1003000 0x1000>; 169 interrupts = <111 2 0 0>; 170 }; 171 bman-portal@10000 { 172 compatible = "fsl,bman-portal"; 173 reg = <0x10000 0x4000>, <0x1004000 0x1000>; 174 interrupts = <113 2 0 0>; 175 }; 176 bman-portal@14000 { 177 compatible = "fsl,bman-portal"; 178 reg = <0x14000 0x4000>, <0x1005000 0x1000>; 179 interrupts = <115 2 0 0>; 180 }; 181 bman-portal@18000 { 182 compatible = "fsl,bman-portal"; 183 reg = <0x18000 0x4000>, <0x1006000 0x1000>; 184 interrupts = <117 2 0 0>; 185 }; 186 bman-portal@1c000 { 187 compatible = "fsl,bman-portal"; 188 reg = <0x1c000 0x4000>, <0x1007000 0x1000>; 189 interrupts = <119 2 0 0>; 190 }; 191 bman-portal@20000 { 192 compatible = "fsl,bman-portal"; 193 reg = <0x20000 0x4000>, <0x1008000 0x1000>; 194 interrupts = <121 2 0 0>; 195 }; 196 bman-portal@24000 { 197 compatible = "fsl,bman-portal"; 198 reg = <0x24000 0x4000>, <0x1009000 0x1000>; 199 interrupts = <123 2 0 0>; 200 }; 201 bman-portal@28000 { 202 compatible = "fsl,bman-portal"; 203 reg = <0x28000 0x4000>, <0x100a000 0x1000>; 204 interrupts = <125 2 0 0>; 205 }; 206 bman-portal@2c000 { 207 compatible = "fsl,bman-portal"; 208 reg = <0x2c000 0x4000>, <0x100b000 0x1000>; 209 interrupts = <127 2 0 0>; 210 }; 211 bman-portal@30000 { 212 compatible = "fsl,bman-portal"; 213 reg = <0x30000 0x4000>, <0x100c000 0x1000>; 214 interrupts = <129 2 0 0>; 215 }; 216 bman-portal@34000 { 217 compatible = "fsl,bman-portal"; 218 reg = <0x34000 0x4000>, <0x100d000 0x1000>; 219 interrupts = <131 2 0 0>; 220 }; 221}; 222 223&qportals { 224 #address-cells = <0x1>; 225 #size-cells = <0x1>; 226 compatible = "simple-bus"; 227 228 qportal0: qman-portal@0 { 229 compatible = "fsl,qman-portal"; 230 reg = <0x0 0x4000>, <0x1000000 0x1000>; 231 interrupts = <104 0x2 0 0>; 232 cell-index = <0x0>; 233 }; 234 qportal1: qman-portal@4000 { 235 compatible = "fsl,qman-portal"; 236 reg = <0x4000 0x4000>, <0x1001000 0x1000>; 237 interrupts = <106 0x2 0 0>; 238 cell-index = <0x1>; 239 }; 240 qportal2: qman-portal@8000 { 241 compatible = "fsl,qman-portal"; 242 reg = <0x8000 0x4000>, <0x1002000 0x1000>; 243 interrupts = <108 0x2 0 0>; 244 cell-index = <0x2>; 245 }; 246 qportal3: qman-portal@c000 { 247 compatible = "fsl,qman-portal"; 248 reg = <0xc000 0x4000>, <0x1003000 0x1000>; 249 interrupts = <110 0x2 0 0>; 250 cell-index = <0x3>; 251 }; 252 qportal4: qman-portal@10000 { 253 compatible = "fsl,qman-portal"; 254 reg = <0x10000 0x4000>, <0x1004000 0x1000>; 255 interrupts = <112 0x2 0 0>; 256 cell-index = <0x4>; 257 }; 258 qportal5: qman-portal@14000 { 259 compatible = "fsl,qman-portal"; 260 reg = <0x14000 0x4000>, <0x1005000 0x1000>; 261 interrupts = <114 0x2 0 0>; 262 cell-index = <0x5>; 263 }; 264 qportal6: qman-portal@18000 { 265 compatible = "fsl,qman-portal"; 266 reg = <0x18000 0x4000>, <0x1006000 0x1000>; 267 interrupts = <116 0x2 0 0>; 268 cell-index = <0x6>; 269 }; 270 qportal7: qman-portal@1c000 { 271 compatible = "fsl,qman-portal"; 272 reg = <0x1c000 0x4000>, <0x1007000 0x1000>; 273 interrupts = <118 0x2 0 0>; 274 cell-index = <0x7>; 275 }; 276 qportal8: qman-portal@20000 { 277 compatible = "fsl,qman-portal"; 278 reg = <0x20000 0x4000>, <0x1008000 0x1000>; 279 interrupts = <120 0x2 0 0>; 280 cell-index = <0x8>; 281 }; 282 qportal9: qman-portal@24000 { 283 compatible = "fsl,qman-portal"; 284 reg = <0x24000 0x4000>, <0x1009000 0x1000>; 285 interrupts = <122 0x2 0 0>; 286 cell-index = <0x9>; 287 }; 288 qportal10: qman-portal@28000 { 289 compatible = "fsl,qman-portal"; 290 reg = <0x28000 0x4000>, <0x100a000 0x1000>; 291 interrupts = <124 0x2 0 0>; 292 cell-index = <0xa>; 293 }; 294 qportal11: qman-portal@2c000 { 295 compatible = "fsl,qman-portal"; 296 reg = <0x2c000 0x4000>, <0x100b000 0x1000>; 297 interrupts = <126 0x2 0 0>; 298 cell-index = <0xb>; 299 }; 300 qportal12: qman-portal@30000 { 301 compatible = "fsl,qman-portal"; 302 reg = <0x30000 0x4000>, <0x100c000 0x1000>; 303 interrupts = <128 0x2 0 0>; 304 cell-index = <0xc>; 305 }; 306 qportal13: qman-portal@34000 { 307 compatible = "fsl,qman-portal"; 308 reg = <0x34000 0x4000>, <0x100d000 0x1000>; 309 interrupts = <130 0x2 0 0>; 310 cell-index = <0xd>; 311 }; 312}; 313 314&soc { 315 #address-cells = <1>; 316 #size-cells = <1>; 317 device_type = "soc"; 318 compatible = "simple-bus"; 319 320 soc-sram-error { 321 compatible = "fsl,soc-sram-error"; 322 interrupts = <16 2 1 2>; 323 }; 324 325 corenet-law@0 { 326 compatible = "fsl,corenet-law"; 327 reg = <0x0 0x1000>; 328 fsl,num-laws = <32>; 329 }; 330 331 ddr1: memory-controller@8000 { 332 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 333 reg = <0x8000 0x1000>; 334 interrupts = <16 2 1 8>; 335 }; 336 337 cpc: l3-cache-controller@10000 { 338 compatible = "fsl,b4-l3-cache-controller", "cache"; 339 reg = <0x10000 0x1000>; 340 interrupts = <16 2 1 4>; 341 }; 342 343 corenet-cf@18000 { 344 compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; 345 reg = <0x18000 0x1000>; 346 interrupts = <16 2 1 0>; 347 fsl,ccf-num-csdids = <32>; 348 fsl,ccf-num-snoopids = <32>; 349 }; 350 351 iommu@20000 { 352 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 353 reg = <0x20000 0x4000>; 354 fsl,portid-mapping = <0x8000>; 355 #address-cells = <1>; 356 #size-cells = <1>; 357 interrupts = < 358 24 2 0 0 359 16 2 1 1>; 360 361 362 /* PCIe, DMA, SRIO */ 363 pamu0: pamu@0 { 364 reg = <0 0x1000>; 365 fsl,primary-cache-geometry = <8 1>; 366 fsl,secondary-cache-geometry = <32 2>; 367 }; 368 369 /* AXI2, Maple */ 370 pamu1: pamu@1000 { 371 reg = <0x1000 0x1000>; 372 fsl,primary-cache-geometry = <32 1>; 373 fsl,secondary-cache-geometry = <32 2>; 374 }; 375 376 /* Q/BMan */ 377 pamu2: pamu@2000 { 378 reg = <0x2000 0x1000>; 379 fsl,primary-cache-geometry = <32 1>; 380 fsl,secondary-cache-geometry = <32 2>; 381 }; 382 383 /* AXI1, FMAN */ 384 pamu3: pamu@3000 { 385 reg = <0x3000 0x1000>; 386 fsl,primary-cache-geometry = <32 1>; 387 fsl,secondary-cache-geometry = <32 2>; 388 }; 389 }; 390 391/include/ "qoriq-mpic4.3.dtsi" 392 393 guts: global-utilities@e0000 { 394 compatible = "fsl,b4-device-config"; 395 reg = <0xe0000 0xe00>; 396 fsl,has-rstcr; 397 fsl,liodn-bits = <12>; 398 }; 399 400/include/ "qoriq-clockgen2.dtsi" 401 clockgen: global-utilities@e1000 { 402 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0"; 403 reg = <0xe1000 0x1000>; 404 405 mux0: mux0@0 { 406 #clock-cells = <0>; 407 reg = <0x0 0x4>; 408 compatible = "fsl,qoriq-core-mux-2.0"; 409 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 410 <&pll1 0>, <&pll1 1>, <&pll1 2>; 411 clock-names = "pll0", "pll0-div2", "pll0-div4", 412 "pll1", "pll1-div2", "pll1-div4"; 413 clock-output-names = "cmux0"; 414 }; 415 }; 416 417 rcpm: global-utilities@e2000 { 418 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0"; 419 reg = <0xe2000 0x1000>; 420 }; 421 422/include/ "elo3-dma-0.dtsi" 423 dma@100300 { 424 fsl,iommu-parent = <&pamu0>; 425 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */ 426 }; 427 428/include/ "elo3-dma-1.dtsi" 429 dma@101300 { 430 fsl,iommu-parent = <&pamu0>; 431 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ 432 }; 433 434/include/ "qonverge-usb2-dr-0.dtsi" 435 usb0: usb@210000 { 436 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 437 fsl,iommu-parent = <&pamu1>; 438 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 439 }; 440 441/include/ "qoriq-espi-0.dtsi" 442 spi@110000 { 443 fsl,espi-num-chipselects = <4>; 444 }; 445 446/include/ "qoriq-esdhc-0.dtsi" 447 sdhc@114000 { 448 sdhci,auto-cmd12; 449 fsl,iommu-parent = <&pamu1>; 450 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ 451 }; 452 453/include/ "qoriq-i2c-0.dtsi" 454/include/ "qoriq-i2c-1.dtsi" 455/include/ "qoriq-duart-0.dtsi" 456/include/ "qoriq-duart-1.dtsi" 457/include/ "qoriq-sec5.3-0.dtsi" 458 459/include/ "qoriq-qman3.dtsi" 460 qman: qman@318000 { 461 interrupts = <16 2 1 28>; 462 }; 463 464/include/ "qoriq-bman1.dtsi" 465 bman: bman@31a000 { 466 interrupts = <16 2 1 29>; 467 }; 468 469 L2: l2-cache-controller@c20000 { 470 compatible = "fsl,b4-l2-cache-controller"; 471 reg = <0xc20000 0x1000>; 472 next-level-cache = <&cpc>; 473 }; 474}; 475