1/* 2 * B4420DS Device Tree Source 3 * 4 * Copyright 2012 - 2014 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of 32 * this software, even if advised of the possibility of such damage. 33 */ 34 35/ { 36 model = "fsl,B4QDS"; 37 compatible = "fsl,B4QDS"; 38 #address-cells = <2>; 39 #size-cells = <2>; 40 interrupt-parent = <&mpic>; 41 42 ifc: localbus@ffe124000 { 43 reg = <0xf 0xfe124000 0 0x2000>; 44 ranges = <0 0 0xf 0xe8000000 0x08000000 45 2 0 0xf 0xff800000 0x00010000 46 3 0 0xf 0xffdf0000 0x00008000>; 47 48 nor@0,0 { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 compatible = "cfi-flash"; 52 reg = <0x0 0x0 0x8000000>; 53 bank-width = <2>; 54 device-width = <1>; 55 }; 56 57 nand@2,0 { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "fsl,ifc-nand"; 61 reg = <0x2 0x0 0x10000>; 62 63 partition@0 { 64 /* This location must not be altered */ 65 /* 1MB for u-boot Bootloader Image */ 66 reg = <0x0 0x00100000>; 67 label = "NAND U-Boot Image"; 68 read-only; 69 }; 70 71 partition@100000 { 72 /* 1MB for DTB Image */ 73 reg = <0x00100000 0x00100000>; 74 label = "NAND DTB Image"; 75 }; 76 77 partition@200000 { 78 /* 10MB for Linux Kernel Image */ 79 reg = <0x00200000 0x00A00000>; 80 label = "NAND Linux Kernel Image"; 81 }; 82 83 partition@c00000 { 84 /* 500MB for Root file System Image */ 85 reg = <0x00c00000 0x1F400000>; 86 label = "NAND RFS Image"; 87 }; 88 }; 89 90 board-control@3,0 { 91 compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis"; 92 reg = <3 0 0x300>; 93 }; 94 }; 95 96 memory { 97 device_type = "memory"; 98 }; 99 100 reserved-memory { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 bman_fbpr: bman-fbpr { 106 size = <0 0x1000000>; 107 alignment = <0 0x1000000>; 108 }; 109 qman_fqd: qman-fqd { 110 size = <0 0x400000>; 111 alignment = <0 0x400000>; 112 }; 113 qman_pfdr: qman-pfdr { 114 size = <0 0x2000000>; 115 alignment = <0 0x2000000>; 116 }; 117 }; 118 119 dcsr: dcsr@f00000000 { 120 ranges = <0x00000000 0xf 0x00000000 0x01052000>; 121 }; 122 123 bportals: bman-portals@ff4000000 { 124 ranges = <0x0 0xf 0xf4000000 0x2000000>; 125 }; 126 127 qportals: qman-portals@ff6000000 { 128 ranges = <0x0 0xf 0xf6000000 0x2000000>; 129 }; 130 131 soc: soc@ffe000000 { 132 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 133 reg = <0xf 0xfe000000 0 0x00001000>; 134 spi@110000 { 135 flash@0 { 136 #address-cells = <1>; 137 #size-cells = <1>; 138 compatible = "sst,sst25wf040"; 139 reg = <0>; 140 spi-max-frequency = <40000000>; /* input clock */ 141 }; 142 }; 143 144 sdhc@114000 { 145 /*Disabled as there is no sdhc connector on B4420QDS board*/ 146 status = "disabled"; 147 }; 148 149 i2c@118000 { 150 mux@77 { 151 compatible = "nxp,pca9547"; 152 reg = <0x77>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 i2c@0 { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 reg = <0>; 160 161 eeprom@50 { 162 compatible = "at24,24c64"; 163 reg = <0x50>; 164 }; 165 eeprom@51 { 166 compatible = "at24,24c256"; 167 reg = <0x51>; 168 }; 169 eeprom@53 { 170 compatible = "at24,24c256"; 171 reg = <0x53>; 172 }; 173 eeprom@57 { 174 compatible = "at24,24c256"; 175 reg = <0x57>; 176 }; 177 rtc@68 { 178 compatible = "dallas,ds3232"; 179 reg = <0x68>; 180 }; 181 }; 182 183 i2c@2 { 184 #address-cells = <1>; 185 #size-cells = <0>; 186 reg = <0x2>; 187 188 ina220@40 { 189 compatible = "ti,ina220"; 190 reg = <0x40>; 191 shunt-resistor = <1000>; 192 }; 193 }; 194 195 i2c@3 { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x3>; 199 200 adt7461@4c { 201 compatible = "adi,adt7461"; 202 reg = <0x4c>; 203 }; 204 }; 205 }; 206 }; 207 208 usb@210000 { 209 dr_mode = "host"; 210 phy_type = "ulpi"; 211 }; 212 213 }; 214 215 pci0: pcie@ffe200000 { 216 reg = <0xf 0xfe200000 0 0x10000>; 217 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 218 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 219 pcie@0 { 220 ranges = <0x02000000 0 0xe0000000 221 0x02000000 0 0xe0000000 222 0 0x20000000 223 224 0x01000000 0 0x00000000 225 0x01000000 0 0x00000000 226 0 0x00010000>; 227 }; 228 }; 229 230}; 231 232/include/ "b4si-post.dtsi" 233