1/* 2 * Device Tree Source for AMCC Canyonlands (460EX) 3 * 4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without 8 * any warranty of any kind, whether express or implied. 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <1>; 16 model = "amcc,canyonlands"; 17 compatible = "amcc,canyonlands"; 18 dcr-parent = <&{/cpus/cpu@0}>; 19 20 aliases { 21 ethernet0 = &EMAC0; 22 ethernet1 = &EMAC1; 23 serial0 = &UART0; 24 serial1 = &UART1; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC,460EX"; 34 reg = <0x00000000>; 35 clock-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */ 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; 39 i-cache-size = <32768>; 40 d-cache-size = <32768>; 41 dcr-controller; 42 dcr-access-method = "native"; 43 next-level-cache = <&L2C0>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 50 }; 51 52 UIC0: interrupt-controller0 { 53 compatible = "ibm,uic-460ex","ibm,uic"; 54 interrupt-controller; 55 cell-index = <0>; 56 dcr-reg = <0x0c0 0x009>; 57 #address-cells = <0>; 58 #size-cells = <0>; 59 #interrupt-cells = <2>; 60 }; 61 62 UIC1: interrupt-controller1 { 63 compatible = "ibm,uic-460ex","ibm,uic"; 64 interrupt-controller; 65 cell-index = <1>; 66 dcr-reg = <0x0d0 0x009>; 67 #address-cells = <0>; 68 #size-cells = <0>; 69 #interrupt-cells = <2>; 70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 71 interrupt-parent = <&UIC0>; 72 }; 73 74 UIC2: interrupt-controller2 { 75 compatible = "ibm,uic-460ex","ibm,uic"; 76 interrupt-controller; 77 cell-index = <2>; 78 dcr-reg = <0x0e0 0x009>; 79 #address-cells = <0>; 80 #size-cells = <0>; 81 #interrupt-cells = <2>; 82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 83 interrupt-parent = <&UIC0>; 84 }; 85 86 UIC3: interrupt-controller3 { 87 compatible = "ibm,uic-460ex","ibm,uic"; 88 interrupt-controller; 89 cell-index = <3>; 90 dcr-reg = <0x0f0 0x009>; 91 #address-cells = <0>; 92 #size-cells = <0>; 93 #interrupt-cells = <2>; 94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 95 interrupt-parent = <&UIC0>; 96 }; 97 98 SDR0: sdr { 99 compatible = "ibm,sdr-460ex"; 100 dcr-reg = <0x00e 0x002>; 101 }; 102 103 CPR0: cpr { 104 compatible = "ibm,cpr-460ex"; 105 dcr-reg = <0x00c 0x002>; 106 }; 107 108 L2C0: l2c { 109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 111 0x030 0x008>; /* L2 cache DCR's */ 112 cache-line-size = <32>; /* 32 bytes */ 113 cache-size = <262144>; /* L2, 256K */ 114 interrupt-parent = <&UIC1>; 115 interrupts = <11 1>; 116 }; 117 118 plb { 119 compatible = "ibm,plb-460ex", "ibm,plb4"; 120 #address-cells = <2>; 121 #size-cells = <1>; 122 ranges; 123 clock-frequency = <0>; /* Filled in by U-Boot */ 124 125 SDRAM0: sdram { 126 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 127 dcr-reg = <0x010 0x002>; 128 }; 129 130 CRYPTO: crypto@180000 { 131 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; 132 reg = <4 0x00180000 0x80400>; 133 interrupt-parent = <&UIC0>; 134 interrupts = <0x1d 0x4>; 135 }; 136 137 MAL0: mcmal { 138 compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 139 dcr-reg = <0x180 0x062>; 140 num-tx-chans = <2>; 141 num-rx-chans = <16>; 142 #address-cells = <0>; 143 #size-cells = <0>; 144 interrupt-parent = <&UIC2>; 145 interrupts = < /*TXEOB*/ 0x6 0x4 146 /*RXEOB*/ 0x7 0x4 147 /*SERR*/ 0x3 0x4 148 /*TXDE*/ 0x4 0x4 149 /*RXDE*/ 0x5 0x4>; 150 }; 151 152 USB0: ehci@bffd0400 { 153 compatible = "ibm,usb-ehci-460ex", "usb-ehci"; 154 interrupt-parent = <&UIC2>; 155 interrupts = <0x1d 4>; 156 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; 157 }; 158 159 USB1: usb@bffd0000 { 160 compatible = "ohci-le"; 161 reg = <4 0xbffd0000 0x60>; 162 interrupt-parent = <&UIC2>; 163 interrupts = <0x1e 4>; 164 }; 165 166 POB0: opb { 167 compatible = "ibm,opb-460ex", "ibm,opb"; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 171 clock-frequency = <0>; /* Filled in by U-Boot */ 172 173 EBC0: ebc { 174 compatible = "ibm,ebc-460ex", "ibm,ebc"; 175 dcr-reg = <0x012 0x002>; 176 #address-cells = <2>; 177 #size-cells = <1>; 178 clock-frequency = <0>; /* Filled in by U-Boot */ 179 /* ranges property is supplied by U-Boot */ 180 interrupts = <0x6 0x4>; 181 interrupt-parent = <&UIC1>; 182 183 nor_flash@0,0 { 184 compatible = "amd,s29gl512n", "cfi-flash"; 185 bank-width = <2>; 186 reg = <0x00000000 0x00000000 0x04000000>; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 partition@0 { 190 label = "kernel"; 191 reg = <0x00000000 0x001e0000>; 192 }; 193 partition@1e0000 { 194 label = "dtb"; 195 reg = <0x001e0000 0x00020000>; 196 }; 197 partition@200000 { 198 label = "ramdisk"; 199 reg = <0x00200000 0x01400000>; 200 }; 201 partition@1600000 { 202 label = "jffs2"; 203 reg = <0x01600000 0x00400000>; 204 }; 205 partition@1a00000 { 206 label = "user"; 207 reg = <0x01a00000 0x02560000>; 208 }; 209 partition@3f60000 { 210 label = "env"; 211 reg = <0x03f60000 0x00040000>; 212 }; 213 partition@3fa0000 { 214 label = "u-boot"; 215 reg = <0x03fa0000 0x00060000>; 216 }; 217 }; 218 219 ndfc@3,0 { 220 compatible = "ibm,ndfc"; 221 reg = <0x00000003 0x00000000 0x00002000>; 222 ccr = <0x00001000>; 223 bank-settings = <0x80002222>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 227 nand { 228 #address-cells = <1>; 229 #size-cells = <1>; 230 231 partition@0 { 232 label = "u-boot"; 233 reg = <0x00000000 0x00100000>; 234 }; 235 partition@100000 { 236 label = "user"; 237 reg = <0x00000000 0x03f00000>; 238 }; 239 }; 240 }; 241 }; 242 243 UART0: serial@ef600300 { 244 device_type = "serial"; 245 compatible = "ns16550"; 246 reg = <0xef600300 0x00000008>; 247 virtual-reg = <0xef600300>; 248 clock-frequency = <0>; /* Filled in by U-Boot */ 249 current-speed = <0>; /* Filled in by U-Boot */ 250 interrupt-parent = <&UIC1>; 251 interrupts = <0x1 0x4>; 252 }; 253 254 UART1: serial@ef600400 { 255 device_type = "serial"; 256 compatible = "ns16550"; 257 reg = <0xef600400 0x00000008>; 258 virtual-reg = <0xef600400>; 259 clock-frequency = <0>; /* Filled in by U-Boot */ 260 current-speed = <0>; /* Filled in by U-Boot */ 261 interrupt-parent = <&UIC0>; 262 interrupts = <0x1 0x4>; 263 }; 264 265 UART2: serial@ef600500 { 266 device_type = "serial"; 267 compatible = "ns16550"; 268 reg = <0xef600500 0x00000008>; 269 virtual-reg = <0xef600500>; 270 clock-frequency = <0>; /* Filled in by U-Boot */ 271 current-speed = <0>; /* Filled in by U-Boot */ 272 interrupt-parent = <&UIC1>; 273 interrupts = <28 0x4>; 274 }; 275 276 UART3: serial@ef600600 { 277 device_type = "serial"; 278 compatible = "ns16550"; 279 reg = <0xef600600 0x00000008>; 280 virtual-reg = <0xef600600>; 281 clock-frequency = <0>; /* Filled in by U-Boot */ 282 current-speed = <0>; /* Filled in by U-Boot */ 283 interrupt-parent = <&UIC1>; 284 interrupts = <29 0x4>; 285 }; 286 287 IIC0: i2c@ef600700 { 288 compatible = "ibm,iic-460ex", "ibm,iic"; 289 reg = <0xef600700 0x00000014>; 290 interrupt-parent = <&UIC0>; 291 interrupts = <0x2 0x4>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 rtc@68 { 295 compatible = "stm,m41t80"; 296 reg = <0x68>; 297 interrupt-parent = <&UIC2>; 298 interrupts = <0x19 0x8>; 299 }; 300 sttm@48 { 301 compatible = "ad,ad7414"; 302 reg = <0x48>; 303 interrupt-parent = <&UIC1>; 304 interrupts = <0x14 0x8>; 305 }; 306 }; 307 308 IIC1: i2c@ef600800 { 309 compatible = "ibm,iic-460ex", "ibm,iic"; 310 reg = <0xef600800 0x00000014>; 311 interrupt-parent = <&UIC0>; 312 interrupts = <0x3 0x4>; 313 }; 314 315 ZMII0: emac-zmii@ef600d00 { 316 compatible = "ibm,zmii-460ex", "ibm,zmii"; 317 reg = <0xef600d00 0x0000000c>; 318 }; 319 320 RGMII0: emac-rgmii@ef601500 { 321 compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 322 reg = <0xef601500 0x00000008>; 323 has-mdio; 324 }; 325 326 TAH0: emac-tah@ef601350 { 327 compatible = "ibm,tah-460ex", "ibm,tah"; 328 reg = <0xef601350 0x00000030>; 329 }; 330 331 TAH1: emac-tah@ef601450 { 332 compatible = "ibm,tah-460ex", "ibm,tah"; 333 reg = <0xef601450 0x00000030>; 334 }; 335 336 EMAC0: ethernet@ef600e00 { 337 device_type = "network"; 338 compatible = "ibm,emac-460ex", "ibm,emac4sync"; 339 interrupt-parent = <&EMAC0>; 340 interrupts = <0x0 0x1>; 341 #interrupt-cells = <1>; 342 #address-cells = <0>; 343 #size-cells = <0>; 344 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 345 /*Wake*/ 0x1 &UIC2 0x14 0x4>; 346 reg = <0xef600e00 0x000000c4>; 347 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 348 mal-device = <&MAL0>; 349 mal-tx-channel = <0>; 350 mal-rx-channel = <0>; 351 cell-index = <0>; 352 max-frame-size = <9000>; 353 rx-fifo-size = <4096>; 354 tx-fifo-size = <2048>; 355 rx-fifo-size-gige = <16384>; 356 phy-mode = "rgmii"; 357 phy-map = <0x00000000>; 358 rgmii-device = <&RGMII0>; 359 rgmii-channel = <0>; 360 tah-device = <&TAH0>; 361 tah-channel = <0>; 362 has-inverted-stacr-oc; 363 has-new-stacr-staopc; 364 }; 365 366 EMAC1: ethernet@ef600f00 { 367 device_type = "network"; 368 compatible = "ibm,emac-460ex", "ibm,emac4sync"; 369 interrupt-parent = <&EMAC1>; 370 interrupts = <0x0 0x1>; 371 #interrupt-cells = <1>; 372 #address-cells = <0>; 373 #size-cells = <0>; 374 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 375 /*Wake*/ 0x1 &UIC2 0x15 0x4>; 376 reg = <0xef600f00 0x000000c4>; 377 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 378 mal-device = <&MAL0>; 379 mal-tx-channel = <1>; 380 mal-rx-channel = <8>; 381 cell-index = <1>; 382 max-frame-size = <9000>; 383 rx-fifo-size = <4096>; 384 tx-fifo-size = <2048>; 385 rx-fifo-size-gige = <16384>; 386 phy-mode = "rgmii"; 387 phy-map = <0x00000000>; 388 rgmii-device = <&RGMII0>; 389 rgmii-channel = <1>; 390 tah-device = <&TAH1>; 391 tah-channel = <1>; 392 has-inverted-stacr-oc; 393 has-new-stacr-staopc; 394 mdio-device = <&EMAC0>; 395 }; 396 }; 397 398 PCIX0: pci@c0ec00000 { 399 device_type = "pci"; 400 #interrupt-cells = <1>; 401 #size-cells = <2>; 402 #address-cells = <3>; 403 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 404 primary; 405 large-inbound-windows; 406 enable-msi-hole; 407 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 408 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 409 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 410 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 411 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 412 413 /* Outbound ranges, one memory and one IO, 414 * later cannot be changed 415 */ 416 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 417 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 418 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 419 420 /* Inbound 2GB range starting at 0 */ 421 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 422 423 /* This drives busses 0 to 0x3f */ 424 bus-range = <0x0 0x3f>; 425 426 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 427 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 428 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 429 }; 430 431 PCIE0: pciex@d00000000 { 432 device_type = "pci"; 433 #interrupt-cells = <1>; 434 #size-cells = <2>; 435 #address-cells = <3>; 436 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 437 primary; 438 port = <0x0>; /* port number */ 439 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 440 0x0000000c 0x08010000 0x00001000>; /* Registers */ 441 dcr-reg = <0x100 0x020>; 442 sdr-base = <0x300>; 443 444 /* Outbound ranges, one memory and one IO, 445 * later cannot be changed 446 */ 447 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 448 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 449 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 450 451 /* Inbound 2GB range starting at 0 */ 452 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 453 454 /* This drives busses 40 to 0x7f */ 455 bus-range = <0x40 0x7f>; 456 457 /* Legacy interrupts (note the weird polarity, the bridge seems 458 * to invert PCIe legacy interrupts). 459 * We are de-swizzling here because the numbers are actually for 460 * port of the root complex virtual P2P bridge. But I want 461 * to avoid putting a node for it in the tree, so the numbers 462 * below are basically de-swizzled numbers. 463 * The real slot is on idsel 0, so the swizzling is 1:1 464 */ 465 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 466 interrupt-map = < 467 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 468 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 469 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 470 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 471 }; 472 473 PCIE1: pciex@d20000000 { 474 device_type = "pci"; 475 #interrupt-cells = <1>; 476 #size-cells = <2>; 477 #address-cells = <3>; 478 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 479 primary; 480 port = <0x1>; /* port number */ 481 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 482 0x0000000c 0x08011000 0x00001000>; /* Registers */ 483 dcr-reg = <0x120 0x020>; 484 sdr-base = <0x340>; 485 486 /* Outbound ranges, one memory and one IO, 487 * later cannot be changed 488 */ 489 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 490 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 491 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 492 493 /* Inbound 2GB range starting at 0 */ 494 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 495 496 /* This drives busses 80 to 0xbf */ 497 bus-range = <0x80 0xbf>; 498 499 /* Legacy interrupts (note the weird polarity, the bridge seems 500 * to invert PCIe legacy interrupts). 501 * We are de-swizzling here because the numbers are actually for 502 * port of the root complex virtual P2P bridge. But I want 503 * to avoid putting a node for it in the tree, so the numbers 504 * below are basically de-swizzled numbers. 505 * The real slot is on idsel 0, so the swizzling is 1:1 506 */ 507 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 508 interrupt-map = < 509 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 510 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 511 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 512 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 513 }; 514 }; 515}; 516