18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 488eeb72eSStefan Roese * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 138bc4a51dSStefan Roese/ { 148bc4a51dSStefan Roese #address-cells = <2>; 158bc4a51dSStefan Roese #size-cells = <1>; 168bc4a51dSStefan Roese model = "amcc,canyonlands"; 178bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 198bc4a51dSStefan Roese 208bc4a51dSStefan Roese aliases { 218bc4a51dSStefan Roese ethernet0 = &EMAC0; 228bc4a51dSStefan Roese ethernet1 = &EMAC1; 238bc4a51dSStefan Roese serial0 = &UART0; 248bc4a51dSStefan Roese serial1 = &UART1; 258bc4a51dSStefan Roese }; 268bc4a51dSStefan Roese 278bc4a51dSStefan Roese cpus { 288bc4a51dSStefan Roese #address-cells = <1>; 298bc4a51dSStefan Roese #size-cells = <0>; 308bc4a51dSStefan Roese 318bc4a51dSStefan Roese cpu@0 { 328bc4a51dSStefan Roese device_type = "cpu"; 338bc4a51dSStefan Roese model = "PowerPC,460EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 358bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 368bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <32768>; 4071f34979SDavid Gibson d-cache-size = <32768>; 418bc4a51dSStefan Roese dcr-controller; 428bc4a51dSStefan Roese dcr-access-method = "native"; 43cd85400aSStefan Roese next-level-cache = <&L2C0>; 448bc4a51dSStefan Roese }; 458bc4a51dSStefan Roese }; 468bc4a51dSStefan Roese 478bc4a51dSStefan Roese memory { 488bc4a51dSStefan Roese device_type = "memory"; 4971f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 508bc4a51dSStefan Roese }; 518bc4a51dSStefan Roese 528bc4a51dSStefan Roese UIC0: interrupt-controller0 { 538bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 548bc4a51dSStefan Roese interrupt-controller; 558bc4a51dSStefan Roese cell-index = <0>; 5671f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 578bc4a51dSStefan Roese #address-cells = <0>; 588bc4a51dSStefan Roese #size-cells = <0>; 598bc4a51dSStefan Roese #interrupt-cells = <2>; 608bc4a51dSStefan Roese }; 618bc4a51dSStefan Roese 628bc4a51dSStefan Roese UIC1: interrupt-controller1 { 638bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 648bc4a51dSStefan Roese interrupt-controller; 658bc4a51dSStefan Roese cell-index = <1>; 6671f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 678bc4a51dSStefan Roese #address-cells = <0>; 688bc4a51dSStefan Roese #size-cells = <0>; 698bc4a51dSStefan Roese #interrupt-cells = <2>; 7071f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 718bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 728bc4a51dSStefan Roese }; 738bc4a51dSStefan Roese 748bc4a51dSStefan Roese UIC2: interrupt-controller2 { 758bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 768bc4a51dSStefan Roese interrupt-controller; 778bc4a51dSStefan Roese cell-index = <2>; 7871f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 798bc4a51dSStefan Roese #address-cells = <0>; 808bc4a51dSStefan Roese #size-cells = <0>; 818bc4a51dSStefan Roese #interrupt-cells = <2>; 8271f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 838bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 848bc4a51dSStefan Roese }; 858bc4a51dSStefan Roese 868bc4a51dSStefan Roese UIC3: interrupt-controller3 { 878bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 888bc4a51dSStefan Roese interrupt-controller; 898bc4a51dSStefan Roese cell-index = <3>; 9071f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 918bc4a51dSStefan Roese #address-cells = <0>; 928bc4a51dSStefan Roese #size-cells = <0>; 938bc4a51dSStefan Roese #interrupt-cells = <2>; 9471f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 958bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 968bc4a51dSStefan Roese }; 978bc4a51dSStefan Roese 988bc4a51dSStefan Roese SDR0: sdr { 998bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 10071f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 1018bc4a51dSStefan Roese }; 1028bc4a51dSStefan Roese 1038bc4a51dSStefan Roese CPR0: cpr { 1048bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 10571f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 1068bc4a51dSStefan Roese }; 1078bc4a51dSStefan Roese 108*ee2ffd8bSVictor Gallardo CPM0: cpm { 109*ee2ffd8bSVictor Gallardo compatible = "ibm,cpm"; 110*ee2ffd8bSVictor Gallardo dcr-access-method = "native"; 111*ee2ffd8bSVictor Gallardo dcr-reg = <0x160 0x003>; 112*ee2ffd8bSVictor Gallardo unused-units = <0x00000100>; 113*ee2ffd8bSVictor Gallardo idle-doze = <0x02000000>; 114*ee2ffd8bSVictor Gallardo standby = <0xfeff791d>; 115*ee2ffd8bSVictor Gallardo }; 116*ee2ffd8bSVictor Gallardo 117cd85400aSStefan Roese L2C0: l2c { 118cd85400aSStefan Roese compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 119cd85400aSStefan Roese dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 120cd85400aSStefan Roese 0x030 0x008>; /* L2 cache DCR's */ 121cd85400aSStefan Roese cache-line-size = <32>; /* 32 bytes */ 122cd85400aSStefan Roese cache-size = <262144>; /* L2, 256K */ 123cd85400aSStefan Roese interrupt-parent = <&UIC1>; 124cd85400aSStefan Roese interrupts = <11 1>; 125cd85400aSStefan Roese }; 126cd85400aSStefan Roese 1278bc4a51dSStefan Roese plb { 1288bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1298bc4a51dSStefan Roese #address-cells = <2>; 1308bc4a51dSStefan Roese #size-cells = <1>; 1318bc4a51dSStefan Roese ranges; 1328bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1338bc4a51dSStefan Roese 1348bc4a51dSStefan Roese SDRAM0: sdram { 1358bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 13671f34979SDavid Gibson dcr-reg = <0x010 0x002>; 1378bc4a51dSStefan Roese }; 1388bc4a51dSStefan Roese 139049359d6SJames Hsiao CRYPTO: crypto@180000 { 140049359d6SJames Hsiao compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; 141049359d6SJames Hsiao reg = <4 0x00180000 0x80400>; 142049359d6SJames Hsiao interrupt-parent = <&UIC0>; 143049359d6SJames Hsiao interrupts = <0x1d 0x4>; 144049359d6SJames Hsiao }; 145049359d6SJames Hsiao 1468bc4a51dSStefan Roese MAL0: mcmal { 1478bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 14871f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1498bc4a51dSStefan Roese num-tx-chans = <2>; 15071f34979SDavid Gibson num-rx-chans = <16>; 1518bc4a51dSStefan Roese #address-cells = <0>; 1528bc4a51dSStefan Roese #size-cells = <0>; 1538bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 15471f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 15571f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 15671f34979SDavid Gibson /*SERR*/ 0x3 0x4 15771f34979SDavid Gibson /*TXDE*/ 0x4 0x4 15871f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 1598bc4a51dSStefan Roese }; 1608bc4a51dSStefan Roese 161018f76ecSBenjamin Herrenschmidt USB0: ehci@bffd0400 { 162018f76ecSBenjamin Herrenschmidt compatible = "ibm,usb-ehci-460ex", "usb-ehci"; 163018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 164018f76ecSBenjamin Herrenschmidt interrupts = <0x1d 4>; 165018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; 166018f76ecSBenjamin Herrenschmidt }; 167018f76ecSBenjamin Herrenschmidt 168018f76ecSBenjamin Herrenschmidt USB1: usb@bffd0000 { 169018f76ecSBenjamin Herrenschmidt compatible = "ohci-le"; 170018f76ecSBenjamin Herrenschmidt reg = <4 0xbffd0000 0x60>; 171018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 172018f76ecSBenjamin Herrenschmidt interrupts = <0x1e 4>; 173018f76ecSBenjamin Herrenschmidt }; 174018f76ecSBenjamin Herrenschmidt 17531fc0bd4SRupjyoti Sarmah SATA0: sata@bffd1000 { 17631fc0bd4SRupjyoti Sarmah compatible = "amcc,sata-460ex"; 17731fc0bd4SRupjyoti Sarmah reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; 17831fc0bd4SRupjyoti Sarmah interrupt-parent = <&UIC3>; 17931fc0bd4SRupjyoti Sarmah interrupts = <0x0 0x4 /* SATA */ 18031fc0bd4SRupjyoti Sarmah 0x5 0x4>; /* AHBDMA */ 18131fc0bd4SRupjyoti Sarmah }; 18231fc0bd4SRupjyoti Sarmah 1838bc4a51dSStefan Roese POB0: opb { 1848bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1858bc4a51dSStefan Roese #address-cells = <1>; 1868bc4a51dSStefan Roese #size-cells = <1>; 18771f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 1888bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1898bc4a51dSStefan Roese 1908bc4a51dSStefan Roese EBC0: ebc { 1918bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 19271f34979SDavid Gibson dcr-reg = <0x012 0x002>; 1938bc4a51dSStefan Roese #address-cells = <2>; 1948bc4a51dSStefan Roese #size-cells = <1>; 1958bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1965020231bSStefan Roese /* ranges property is supplied by U-Boot */ 19771f34979SDavid Gibson interrupts = <0x6 0x4>; 1988bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1995020231bSStefan Roese 2005020231bSStefan Roese nor_flash@0,0 { 2015020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 2025020231bSStefan Roese bank-width = <2>; 20371f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 2045020231bSStefan Roese #address-cells = <1>; 2055020231bSStefan Roese #size-cells = <1>; 2065020231bSStefan Roese partition@0 { 2075020231bSStefan Roese label = "kernel"; 20871f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 2095020231bSStefan Roese }; 2105020231bSStefan Roese partition@1e0000 { 2115020231bSStefan Roese label = "dtb"; 21271f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 2135020231bSStefan Roese }; 2145020231bSStefan Roese partition@200000 { 2155020231bSStefan Roese label = "ramdisk"; 21671f34979SDavid Gibson reg = <0x00200000 0x01400000>; 2175020231bSStefan Roese }; 2185020231bSStefan Roese partition@1600000 { 2195020231bSStefan Roese label = "jffs2"; 22071f34979SDavid Gibson reg = <0x01600000 0x00400000>; 2215020231bSStefan Roese }; 2225020231bSStefan Roese partition@1a00000 { 2235020231bSStefan Roese label = "user"; 22471f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 2255020231bSStefan Roese }; 2265020231bSStefan Roese partition@3f60000 { 2275020231bSStefan Roese label = "env"; 22871f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 2295020231bSStefan Roese }; 2305020231bSStefan Roese partition@3fa0000 { 2315020231bSStefan Roese label = "u-boot"; 23271f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 2335020231bSStefan Roese }; 2345020231bSStefan Roese }; 23588eeb72eSStefan Roese 23688eeb72eSStefan Roese ndfc@3,0 { 23788eeb72eSStefan Roese compatible = "ibm,ndfc"; 23888eeb72eSStefan Roese reg = <0x00000003 0x00000000 0x00002000>; 23988eeb72eSStefan Roese ccr = <0x00001000>; 24088eeb72eSStefan Roese bank-settings = <0x80002222>; 24188eeb72eSStefan Roese #address-cells = <1>; 24288eeb72eSStefan Roese #size-cells = <1>; 24388eeb72eSStefan Roese 24488eeb72eSStefan Roese nand { 24588eeb72eSStefan Roese #address-cells = <1>; 24688eeb72eSStefan Roese #size-cells = <1>; 24788eeb72eSStefan Roese 24888eeb72eSStefan Roese partition@0 { 24988eeb72eSStefan Roese label = "u-boot"; 25088eeb72eSStefan Roese reg = <0x00000000 0x00100000>; 25188eeb72eSStefan Roese }; 25288eeb72eSStefan Roese partition@100000 { 25388eeb72eSStefan Roese label = "user"; 25488eeb72eSStefan Roese reg = <0x00000000 0x03f00000>; 25588eeb72eSStefan Roese }; 25688eeb72eSStefan Roese }; 25788eeb72eSStefan Roese }; 2588bc4a51dSStefan Roese }; 2598bc4a51dSStefan Roese 2608bc4a51dSStefan Roese UART0: serial@ef600300 { 2618bc4a51dSStefan Roese device_type = "serial"; 2628bc4a51dSStefan Roese compatible = "ns16550"; 26371f34979SDavid Gibson reg = <0xef600300 0x00000008>; 26471f34979SDavid Gibson virtual-reg = <0xef600300>; 2658bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2668bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2678bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 26871f34979SDavid Gibson interrupts = <0x1 0x4>; 2698bc4a51dSStefan Roese }; 2708bc4a51dSStefan Roese 2718bc4a51dSStefan Roese UART1: serial@ef600400 { 2728bc4a51dSStefan Roese device_type = "serial"; 2738bc4a51dSStefan Roese compatible = "ns16550"; 27471f34979SDavid Gibson reg = <0xef600400 0x00000008>; 27571f34979SDavid Gibson virtual-reg = <0xef600400>; 2768bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2778bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2788bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 27971f34979SDavid Gibson interrupts = <0x1 0x4>; 2808bc4a51dSStefan Roese }; 2818bc4a51dSStefan Roese 2828bc4a51dSStefan Roese IIC0: i2c@ef600700 { 2838bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 28471f34979SDavid Gibson reg = <0xef600700 0x00000014>; 2858bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 28671f34979SDavid Gibson interrupts = <0x2 0x4>; 287018f76ecSBenjamin Herrenschmidt #address-cells = <1>; 288018f76ecSBenjamin Herrenschmidt #size-cells = <0>; 289018f76ecSBenjamin Herrenschmidt rtc@68 { 290018f76ecSBenjamin Herrenschmidt compatible = "stm,m41t80"; 291018f76ecSBenjamin Herrenschmidt reg = <0x68>; 292018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC2>; 293018f76ecSBenjamin Herrenschmidt interrupts = <0x19 0x8>; 294018f76ecSBenjamin Herrenschmidt }; 295018f76ecSBenjamin Herrenschmidt sttm@48 { 296018f76ecSBenjamin Herrenschmidt compatible = "ad,ad7414"; 297018f76ecSBenjamin Herrenschmidt reg = <0x48>; 298018f76ecSBenjamin Herrenschmidt interrupt-parent = <&UIC1>; 299018f76ecSBenjamin Herrenschmidt interrupts = <0x14 0x8>; 300018f76ecSBenjamin Herrenschmidt }; 3018bc4a51dSStefan Roese }; 3028bc4a51dSStefan Roese 3038bc4a51dSStefan Roese IIC1: i2c@ef600800 { 3048bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 30571f34979SDavid Gibson reg = <0xef600800 0x00000014>; 3068bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 30771f34979SDavid Gibson interrupts = <0x3 0x4>; 3088bc4a51dSStefan Roese }; 3098bc4a51dSStefan Roese 3108bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 3118bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 31271f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 3138bc4a51dSStefan Roese }; 3148bc4a51dSStefan Roese 3158bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 3168bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 31771f34979SDavid Gibson reg = <0xef601500 0x00000008>; 3188bc4a51dSStefan Roese has-mdio; 3198bc4a51dSStefan Roese }; 3208bc4a51dSStefan Roese 321a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 322a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 32371f34979SDavid Gibson reg = <0xef601350 0x00000030>; 324a6190a84SStefan Roese }; 325a6190a84SStefan Roese 326a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 327a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 32871f34979SDavid Gibson reg = <0xef601450 0x00000030>; 329a6190a84SStefan Roese }; 330a6190a84SStefan Roese 3318bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 3328bc4a51dSStefan Roese device_type = "network"; 33305781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3348bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 33571f34979SDavid Gibson interrupts = <0x0 0x1>; 3368bc4a51dSStefan Roese #interrupt-cells = <1>; 3378bc4a51dSStefan Roese #address-cells = <0>; 3388bc4a51dSStefan Roese #size-cells = <0>; 33971f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 34071f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 34105781ccdSGrant Erickson reg = <0xef600e00 0x000000c4>; 3428bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3438bc4a51dSStefan Roese mal-device = <&MAL0>; 3448bc4a51dSStefan Roese mal-tx-channel = <0>; 3458bc4a51dSStefan Roese mal-rx-channel = <0>; 3468bc4a51dSStefan Roese cell-index = <0>; 34771f34979SDavid Gibson max-frame-size = <9000>; 34871f34979SDavid Gibson rx-fifo-size = <4096>; 34971f34979SDavid Gibson tx-fifo-size = <2048>; 350835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 3518bc4a51dSStefan Roese phy-mode = "rgmii"; 35271f34979SDavid Gibson phy-map = <0x00000000>; 3538bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3548bc4a51dSStefan Roese rgmii-channel = <0>; 355a6190a84SStefan Roese tah-device = <&TAH0>; 356a6190a84SStefan Roese tah-channel = <0>; 3578bc4a51dSStefan Roese has-inverted-stacr-oc; 3588bc4a51dSStefan Roese has-new-stacr-staopc; 3598bc4a51dSStefan Roese }; 3608bc4a51dSStefan Roese 3618bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 3628bc4a51dSStefan Roese device_type = "network"; 36305781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3648bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 36571f34979SDavid Gibson interrupts = <0x0 0x1>; 3668bc4a51dSStefan Roese #interrupt-cells = <1>; 3678bc4a51dSStefan Roese #address-cells = <0>; 3688bc4a51dSStefan Roese #size-cells = <0>; 36971f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 37071f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 37105781ccdSGrant Erickson reg = <0xef600f00 0x000000c4>; 3728bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3738bc4a51dSStefan Roese mal-device = <&MAL0>; 3748bc4a51dSStefan Roese mal-tx-channel = <1>; 3758bc4a51dSStefan Roese mal-rx-channel = <8>; 3768bc4a51dSStefan Roese cell-index = <1>; 37771f34979SDavid Gibson max-frame-size = <9000>; 37871f34979SDavid Gibson rx-fifo-size = <4096>; 37971f34979SDavid Gibson tx-fifo-size = <2048>; 380835ad8e7SDave Mitchell rx-fifo-size-gige = <16384>; 3818bc4a51dSStefan Roese phy-mode = "rgmii"; 38271f34979SDavid Gibson phy-map = <0x00000000>; 3838bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3848bc4a51dSStefan Roese rgmii-channel = <1>; 385a6190a84SStefan Roese tah-device = <&TAH1>; 386a6190a84SStefan Roese tah-channel = <1>; 3878bc4a51dSStefan Roese has-inverted-stacr-oc; 3888bc4a51dSStefan Roese has-new-stacr-staopc; 389a6190a84SStefan Roese mdio-device = <&EMAC0>; 3908bc4a51dSStefan Roese }; 3918bc4a51dSStefan Roese }; 3928bc4a51dSStefan Roese 3938bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 3948bc4a51dSStefan Roese device_type = "pci"; 3958bc4a51dSStefan Roese #interrupt-cells = <1>; 3968bc4a51dSStefan Roese #size-cells = <2>; 3978bc4a51dSStefan Roese #address-cells = <3>; 3988bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 3998bc4a51dSStefan Roese primary; 4008bc4a51dSStefan Roese large-inbound-windows; 4018bc4a51dSStefan Roese enable-msi-hole; 40271f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 40371f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 40471f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 40571f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 40671f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 4078bc4a51dSStefan Roese 4088bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4098bc4a51dSStefan Roese * later cannot be changed 4108bc4a51dSStefan Roese */ 41171f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 41284d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 41371f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 4148bc4a51dSStefan Roese 4158bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 41671f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4178bc4a51dSStefan Roese 4188bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 41971f34979SDavid Gibson bus-range = <0x0 0x3f>; 4208bc4a51dSStefan Roese 4218bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 42271f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 42371f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 4248bc4a51dSStefan Roese }; 4258bc4a51dSStefan Roese 4268bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 4278bc4a51dSStefan Roese device_type = "pci"; 4288bc4a51dSStefan Roese #interrupt-cells = <1>; 4298bc4a51dSStefan Roese #size-cells = <2>; 4308bc4a51dSStefan Roese #address-cells = <3>; 4318bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4328bc4a51dSStefan Roese primary; 43371f34979SDavid Gibson port = <0x0>; /* port number */ 43471f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 43571f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 43671f34979SDavid Gibson dcr-reg = <0x100 0x020>; 43771f34979SDavid Gibson sdr-base = <0x300>; 4388bc4a51dSStefan Roese 4398bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4408bc4a51dSStefan Roese * later cannot be changed 4418bc4a51dSStefan Roese */ 44271f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 44384d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 44471f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 4458bc4a51dSStefan Roese 4468bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 44771f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4488bc4a51dSStefan Roese 4498bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 45071f34979SDavid Gibson bus-range = <0x40 0x7f>; 4518bc4a51dSStefan Roese 4528bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4538bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4548bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4558bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4568bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4578bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4588bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4598bc4a51dSStefan Roese */ 46071f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4618bc4a51dSStefan Roese interrupt-map = < 46271f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 46371f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 46471f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 46571f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 4668bc4a51dSStefan Roese }; 4678bc4a51dSStefan Roese 4688bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 4698bc4a51dSStefan Roese device_type = "pci"; 4708bc4a51dSStefan Roese #interrupt-cells = <1>; 4718bc4a51dSStefan Roese #size-cells = <2>; 4728bc4a51dSStefan Roese #address-cells = <3>; 4738bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4748bc4a51dSStefan Roese primary; 47571f34979SDavid Gibson port = <0x1>; /* port number */ 47671f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 47771f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 47871f34979SDavid Gibson dcr-reg = <0x120 0x020>; 47971f34979SDavid Gibson sdr-base = <0x340>; 4808bc4a51dSStefan Roese 4818bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4828bc4a51dSStefan Roese * later cannot be changed 4838bc4a51dSStefan Roese */ 48471f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 48584d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 48671f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 4878bc4a51dSStefan Roese 4888bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 48971f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4908bc4a51dSStefan Roese 4918bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 49271f34979SDavid Gibson bus-range = <0x80 0xbf>; 4938bc4a51dSStefan Roese 4948bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4958bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4968bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4978bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4988bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4998bc4a51dSStefan Roese * below are basically de-swizzled numbers. 5008bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 5018bc4a51dSStefan Roese */ 50271f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 5038bc4a51dSStefan Roese interrupt-map = < 50471f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 50571f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 50671f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 50771f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 5088bc4a51dSStefan Roese }; 5098bc4a51dSStefan Roese }; 5108bc4a51dSStefan Roese}; 511