1*8bc4a51dSStefan Roese/* 2*8bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 3*8bc4a51dSStefan Roese * 4*8bc4a51dSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 5*8bc4a51dSStefan Roese * 6*8bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 7*8bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 8*8bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 9*8bc4a51dSStefan Roese */ 10*8bc4a51dSStefan Roese 11*8bc4a51dSStefan Roese/ { 12*8bc4a51dSStefan Roese #address-cells = <2>; 13*8bc4a51dSStefan Roese #size-cells = <1>; 14*8bc4a51dSStefan Roese model = "amcc,canyonlands"; 15*8bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 16*8bc4a51dSStefan Roese dcr-parent = <&/cpus/cpu@0>; 17*8bc4a51dSStefan Roese 18*8bc4a51dSStefan Roese aliases { 19*8bc4a51dSStefan Roese ethernet0 = &EMAC0; 20*8bc4a51dSStefan Roese ethernet1 = &EMAC1; 21*8bc4a51dSStefan Roese serial0 = &UART0; 22*8bc4a51dSStefan Roese serial1 = &UART1; 23*8bc4a51dSStefan Roese }; 24*8bc4a51dSStefan Roese 25*8bc4a51dSStefan Roese cpus { 26*8bc4a51dSStefan Roese #address-cells = <1>; 27*8bc4a51dSStefan Roese #size-cells = <0>; 28*8bc4a51dSStefan Roese 29*8bc4a51dSStefan Roese cpu@0 { 30*8bc4a51dSStefan Roese device_type = "cpu"; 31*8bc4a51dSStefan Roese model = "PowerPC,460EX"; 32*8bc4a51dSStefan Roese reg = <0>; 33*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 34*8bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 35*8bc4a51dSStefan Roese i-cache-line-size = <20>; 36*8bc4a51dSStefan Roese d-cache-line-size = <20>; 37*8bc4a51dSStefan Roese i-cache-size = <8000>; 38*8bc4a51dSStefan Roese d-cache-size = <8000>; 39*8bc4a51dSStefan Roese dcr-controller; 40*8bc4a51dSStefan Roese dcr-access-method = "native"; 41*8bc4a51dSStefan Roese }; 42*8bc4a51dSStefan Roese }; 43*8bc4a51dSStefan Roese 44*8bc4a51dSStefan Roese memory { 45*8bc4a51dSStefan Roese device_type = "memory"; 46*8bc4a51dSStefan Roese reg = <0 0 0>; /* Filled in by U-Boot */ 47*8bc4a51dSStefan Roese }; 48*8bc4a51dSStefan Roese 49*8bc4a51dSStefan Roese UIC0: interrupt-controller0 { 50*8bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 51*8bc4a51dSStefan Roese interrupt-controller; 52*8bc4a51dSStefan Roese cell-index = <0>; 53*8bc4a51dSStefan Roese dcr-reg = <0c0 009>; 54*8bc4a51dSStefan Roese #address-cells = <0>; 55*8bc4a51dSStefan Roese #size-cells = <0>; 56*8bc4a51dSStefan Roese #interrupt-cells = <2>; 57*8bc4a51dSStefan Roese }; 58*8bc4a51dSStefan Roese 59*8bc4a51dSStefan Roese UIC1: interrupt-controller1 { 60*8bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 61*8bc4a51dSStefan Roese interrupt-controller; 62*8bc4a51dSStefan Roese cell-index = <1>; 63*8bc4a51dSStefan Roese dcr-reg = <0d0 009>; 64*8bc4a51dSStefan Roese #address-cells = <0>; 65*8bc4a51dSStefan Roese #size-cells = <0>; 66*8bc4a51dSStefan Roese #interrupt-cells = <2>; 67*8bc4a51dSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 68*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 69*8bc4a51dSStefan Roese }; 70*8bc4a51dSStefan Roese 71*8bc4a51dSStefan Roese UIC2: interrupt-controller2 { 72*8bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 73*8bc4a51dSStefan Roese interrupt-controller; 74*8bc4a51dSStefan Roese cell-index = <2>; 75*8bc4a51dSStefan Roese dcr-reg = <0e0 009>; 76*8bc4a51dSStefan Roese #address-cells = <0>; 77*8bc4a51dSStefan Roese #size-cells = <0>; 78*8bc4a51dSStefan Roese #interrupt-cells = <2>; 79*8bc4a51dSStefan Roese interrupts = <a 4 b 4>; /* cascade */ 80*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 81*8bc4a51dSStefan Roese }; 82*8bc4a51dSStefan Roese 83*8bc4a51dSStefan Roese UIC3: interrupt-controller3 { 84*8bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 85*8bc4a51dSStefan Roese interrupt-controller; 86*8bc4a51dSStefan Roese cell-index = <3>; 87*8bc4a51dSStefan Roese dcr-reg = <0f0 009>; 88*8bc4a51dSStefan Roese #address-cells = <0>; 89*8bc4a51dSStefan Roese #size-cells = <0>; 90*8bc4a51dSStefan Roese #interrupt-cells = <2>; 91*8bc4a51dSStefan Roese interrupts = <10 4 11 4>; /* cascade */ 92*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 93*8bc4a51dSStefan Roese }; 94*8bc4a51dSStefan Roese 95*8bc4a51dSStefan Roese SDR0: sdr { 96*8bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 97*8bc4a51dSStefan Roese dcr-reg = <00e 002>; 98*8bc4a51dSStefan Roese }; 99*8bc4a51dSStefan Roese 100*8bc4a51dSStefan Roese CPR0: cpr { 101*8bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 102*8bc4a51dSStefan Roese dcr-reg = <00c 002>; 103*8bc4a51dSStefan Roese }; 104*8bc4a51dSStefan Roese 105*8bc4a51dSStefan Roese plb { 106*8bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 107*8bc4a51dSStefan Roese #address-cells = <2>; 108*8bc4a51dSStefan Roese #size-cells = <1>; 109*8bc4a51dSStefan Roese ranges; 110*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 111*8bc4a51dSStefan Roese 112*8bc4a51dSStefan Roese SDRAM0: sdram { 113*8bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 114*8bc4a51dSStefan Roese dcr-reg = <010 2>; 115*8bc4a51dSStefan Roese }; 116*8bc4a51dSStefan Roese 117*8bc4a51dSStefan Roese MAL0: mcmal { 118*8bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 119*8bc4a51dSStefan Roese dcr-reg = <180 62>; 120*8bc4a51dSStefan Roese num-tx-chans = <2>; 121*8bc4a51dSStefan Roese num-rx-chans = <10>; 122*8bc4a51dSStefan Roese #address-cells = <0>; 123*8bc4a51dSStefan Roese #size-cells = <0>; 124*8bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 125*8bc4a51dSStefan Roese interrupts = < /*TXEOB*/ 6 4 126*8bc4a51dSStefan Roese /*RXEOB*/ 7 4 127*8bc4a51dSStefan Roese /*SERR*/ 3 4 128*8bc4a51dSStefan Roese /*TXDE*/ 4 4 129*8bc4a51dSStefan Roese /*RXDE*/ 5 4>; 130*8bc4a51dSStefan Roese }; 131*8bc4a51dSStefan Roese 132*8bc4a51dSStefan Roese POB0: opb { 133*8bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 134*8bc4a51dSStefan Roese #address-cells = <1>; 135*8bc4a51dSStefan Roese #size-cells = <1>; 136*8bc4a51dSStefan Roese ranges = <b0000000 4 b0000000 50000000>; 137*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 138*8bc4a51dSStefan Roese 139*8bc4a51dSStefan Roese EBC0: ebc { 140*8bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 141*8bc4a51dSStefan Roese dcr-reg = <012 2>; 142*8bc4a51dSStefan Roese #address-cells = <2>; 143*8bc4a51dSStefan Roese #size-cells = <1>; 144*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 145*8bc4a51dSStefan Roese interrupts = <6 4>; 146*8bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 147*8bc4a51dSStefan Roese }; 148*8bc4a51dSStefan Roese 149*8bc4a51dSStefan Roese UART0: serial@ef600300 { 150*8bc4a51dSStefan Roese device_type = "serial"; 151*8bc4a51dSStefan Roese compatible = "ns16550"; 152*8bc4a51dSStefan Roese reg = <ef600300 8>; 153*8bc4a51dSStefan Roese virtual-reg = <ef600300>; 154*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 155*8bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 156*8bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 157*8bc4a51dSStefan Roese interrupts = <1 4>; 158*8bc4a51dSStefan Roese }; 159*8bc4a51dSStefan Roese 160*8bc4a51dSStefan Roese UART1: serial@ef600400 { 161*8bc4a51dSStefan Roese device_type = "serial"; 162*8bc4a51dSStefan Roese compatible = "ns16550"; 163*8bc4a51dSStefan Roese reg = <ef600400 8>; 164*8bc4a51dSStefan Roese virtual-reg = <ef600400>; 165*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 166*8bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 167*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 168*8bc4a51dSStefan Roese interrupts = <1 4>; 169*8bc4a51dSStefan Roese }; 170*8bc4a51dSStefan Roese 171*8bc4a51dSStefan Roese UART2: serial@ef600500 { 172*8bc4a51dSStefan Roese device_type = "serial"; 173*8bc4a51dSStefan Roese compatible = "ns16550"; 174*8bc4a51dSStefan Roese reg = <ef600500 8>; 175*8bc4a51dSStefan Roese virtual-reg = <ef600500>; 176*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 177*8bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 178*8bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 179*8bc4a51dSStefan Roese interrupts = <1d 4>; 180*8bc4a51dSStefan Roese }; 181*8bc4a51dSStefan Roese 182*8bc4a51dSStefan Roese UART3: serial@ef600600 { 183*8bc4a51dSStefan Roese device_type = "serial"; 184*8bc4a51dSStefan Roese compatible = "ns16550"; 185*8bc4a51dSStefan Roese reg = <ef600600 8>; 186*8bc4a51dSStefan Roese virtual-reg = <ef600600>; 187*8bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 188*8bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 189*8bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 190*8bc4a51dSStefan Roese interrupts = <1e 4>; 191*8bc4a51dSStefan Roese }; 192*8bc4a51dSStefan Roese 193*8bc4a51dSStefan Roese IIC0: i2c@ef600700 { 194*8bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 195*8bc4a51dSStefan Roese reg = <ef600700 14>; 196*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 197*8bc4a51dSStefan Roese interrupts = <2 4>; 198*8bc4a51dSStefan Roese }; 199*8bc4a51dSStefan Roese 200*8bc4a51dSStefan Roese IIC1: i2c@ef600800 { 201*8bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 202*8bc4a51dSStefan Roese reg = <ef600800 14>; 203*8bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 204*8bc4a51dSStefan Roese interrupts = <3 4>; 205*8bc4a51dSStefan Roese }; 206*8bc4a51dSStefan Roese 207*8bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 208*8bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 209*8bc4a51dSStefan Roese reg = <ef600d00 c>; 210*8bc4a51dSStefan Roese }; 211*8bc4a51dSStefan Roese 212*8bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 213*8bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 214*8bc4a51dSStefan Roese reg = <ef601500 8>; 215*8bc4a51dSStefan Roese has-mdio; 216*8bc4a51dSStefan Roese }; 217*8bc4a51dSStefan Roese 218*8bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 219*8bc4a51dSStefan Roese device_type = "network"; 220*8bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 221*8bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 222*8bc4a51dSStefan Roese interrupts = <0 1>; 223*8bc4a51dSStefan Roese #interrupt-cells = <1>; 224*8bc4a51dSStefan Roese #address-cells = <0>; 225*8bc4a51dSStefan Roese #size-cells = <0>; 226*8bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 10 4 227*8bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 14 4>; 228*8bc4a51dSStefan Roese reg = <ef600e00 70>; 229*8bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 230*8bc4a51dSStefan Roese mal-device = <&MAL0>; 231*8bc4a51dSStefan Roese mal-tx-channel = <0>; 232*8bc4a51dSStefan Roese mal-rx-channel = <0>; 233*8bc4a51dSStefan Roese cell-index = <0>; 234*8bc4a51dSStefan Roese max-frame-size = <2328>; 235*8bc4a51dSStefan Roese rx-fifo-size = <1000>; 236*8bc4a51dSStefan Roese tx-fifo-size = <800>; 237*8bc4a51dSStefan Roese phy-mode = "rgmii"; 238*8bc4a51dSStefan Roese phy-map = <00000000>; 239*8bc4a51dSStefan Roese zmii-device = <&ZMII0>; 240*8bc4a51dSStefan Roese zmii-channel = <0>; 241*8bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 242*8bc4a51dSStefan Roese rgmii-channel = <0>; 243*8bc4a51dSStefan Roese has-inverted-stacr-oc; 244*8bc4a51dSStefan Roese has-new-stacr-staopc; 245*8bc4a51dSStefan Roese }; 246*8bc4a51dSStefan Roese 247*8bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 248*8bc4a51dSStefan Roese device_type = "network"; 249*8bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 250*8bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 251*8bc4a51dSStefan Roese interrupts = <0 1>; 252*8bc4a51dSStefan Roese #interrupt-cells = <1>; 253*8bc4a51dSStefan Roese #address-cells = <0>; 254*8bc4a51dSStefan Roese #size-cells = <0>; 255*8bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 11 4 256*8bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 15 4>; 257*8bc4a51dSStefan Roese reg = <ef600f00 70>; 258*8bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 259*8bc4a51dSStefan Roese mal-device = <&MAL0>; 260*8bc4a51dSStefan Roese mal-tx-channel = <1>; 261*8bc4a51dSStefan Roese mal-rx-channel = <8>; 262*8bc4a51dSStefan Roese cell-index = <1>; 263*8bc4a51dSStefan Roese max-frame-size = <2328>; 264*8bc4a51dSStefan Roese rx-fifo-size = <1000>; 265*8bc4a51dSStefan Roese tx-fifo-size = <800>; 266*8bc4a51dSStefan Roese phy-mode = "rgmii"; 267*8bc4a51dSStefan Roese phy-map = <00000000>; 268*8bc4a51dSStefan Roese zmii-device = <&ZMII0>; 269*8bc4a51dSStefan Roese zmii-channel = <1>; 270*8bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 271*8bc4a51dSStefan Roese rgmii-channel = <1>; 272*8bc4a51dSStefan Roese has-inverted-stacr-oc; 273*8bc4a51dSStefan Roese has-new-stacr-staopc; 274*8bc4a51dSStefan Roese }; 275*8bc4a51dSStefan Roese }; 276*8bc4a51dSStefan Roese 277*8bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 278*8bc4a51dSStefan Roese device_type = "pci"; 279*8bc4a51dSStefan Roese #interrupt-cells = <1>; 280*8bc4a51dSStefan Roese #size-cells = <2>; 281*8bc4a51dSStefan Roese #address-cells = <3>; 282*8bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 283*8bc4a51dSStefan Roese primary; 284*8bc4a51dSStefan Roese large-inbound-windows; 285*8bc4a51dSStefan Roese enable-msi-hole; 286*8bc4a51dSStefan Roese reg = <c 0ec00000 8 /* Config space access */ 287*8bc4a51dSStefan Roese 0 0 0 /* no IACK cycles */ 288*8bc4a51dSStefan Roese c 0ed00000 4 /* Special cycles */ 289*8bc4a51dSStefan Roese c 0ec80000 100 /* Internal registers */ 290*8bc4a51dSStefan Roese c 0ec80100 fc>; /* Internal messaging registers */ 291*8bc4a51dSStefan Roese 292*8bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 293*8bc4a51dSStefan Roese * later cannot be changed 294*8bc4a51dSStefan Roese */ 295*8bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 296*8bc4a51dSStefan Roese 01000000 0 00000000 0000000c 08000000 0 00010000>; 297*8bc4a51dSStefan Roese 298*8bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 299*8bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 300*8bc4a51dSStefan Roese 301*8bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 302*8bc4a51dSStefan Roese bus-range = <0 3f>; 303*8bc4a51dSStefan Roese 304*8bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 305*8bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 0>; 306*8bc4a51dSStefan Roese interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 307*8bc4a51dSStefan Roese }; 308*8bc4a51dSStefan Roese 309*8bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 310*8bc4a51dSStefan Roese device_type = "pci"; 311*8bc4a51dSStefan Roese #interrupt-cells = <1>; 312*8bc4a51dSStefan Roese #size-cells = <2>; 313*8bc4a51dSStefan Roese #address-cells = <3>; 314*8bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 315*8bc4a51dSStefan Roese primary; 316*8bc4a51dSStefan Roese port = <0>; /* port number */ 317*8bc4a51dSStefan Roese reg = <d 00000000 20000000 /* Config space access */ 318*8bc4a51dSStefan Roese c 08010000 00001000>; /* Registers */ 319*8bc4a51dSStefan Roese dcr-reg = <100 020>; 320*8bc4a51dSStefan Roese sdr-base = <300>; 321*8bc4a51dSStefan Roese 322*8bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 323*8bc4a51dSStefan Roese * later cannot be changed 324*8bc4a51dSStefan Roese */ 325*8bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 326*8bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80000000 0 00010000>; 327*8bc4a51dSStefan Roese 328*8bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 329*8bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 330*8bc4a51dSStefan Roese 331*8bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 332*8bc4a51dSStefan Roese bus-range = <40 7f>; 333*8bc4a51dSStefan Roese 334*8bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 335*8bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 336*8bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 337*8bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 338*8bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 339*8bc4a51dSStefan Roese * below are basically de-swizzled numbers. 340*8bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 341*8bc4a51dSStefan Roese */ 342*8bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 343*8bc4a51dSStefan Roese interrupt-map = < 344*8bc4a51dSStefan Roese 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 345*8bc4a51dSStefan Roese 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 346*8bc4a51dSStefan Roese 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 347*8bc4a51dSStefan Roese 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 348*8bc4a51dSStefan Roese }; 349*8bc4a51dSStefan Roese 350*8bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 351*8bc4a51dSStefan Roese device_type = "pci"; 352*8bc4a51dSStefan Roese #interrupt-cells = <1>; 353*8bc4a51dSStefan Roese #size-cells = <2>; 354*8bc4a51dSStefan Roese #address-cells = <3>; 355*8bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 356*8bc4a51dSStefan Roese primary; 357*8bc4a51dSStefan Roese port = <1>; /* port number */ 358*8bc4a51dSStefan Roese reg = <d 20000000 20000000 /* Config space access */ 359*8bc4a51dSStefan Roese c 08011000 00001000>; /* Registers */ 360*8bc4a51dSStefan Roese dcr-reg = <120 020>; 361*8bc4a51dSStefan Roese sdr-base = <340>; 362*8bc4a51dSStefan Roese 363*8bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 364*8bc4a51dSStefan Roese * later cannot be changed 365*8bc4a51dSStefan Roese */ 366*8bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 367*8bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80010000 0 00010000>; 368*8bc4a51dSStefan Roese 369*8bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 370*8bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 371*8bc4a51dSStefan Roese 372*8bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 373*8bc4a51dSStefan Roese bus-range = <80 bf>; 374*8bc4a51dSStefan Roese 375*8bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 376*8bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 377*8bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 378*8bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 379*8bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 380*8bc4a51dSStefan Roese * below are basically de-swizzled numbers. 381*8bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 382*8bc4a51dSStefan Roese */ 383*8bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 384*8bc4a51dSStefan Roese interrupt-map = < 385*8bc4a51dSStefan Roese 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 386*8bc4a51dSStefan Roese 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 387*8bc4a51dSStefan Roese 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 388*8bc4a51dSStefan Roese 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 389*8bc4a51dSStefan Roese }; 390*8bc4a51dSStefan Roese }; 391*8bc4a51dSStefan Roese}; 392