18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 48bc4a51dSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 11*71f34979SDavid Gibson/dts-v1/; 12*71f34979SDavid Gibson 138bc4a51dSStefan Roese/ { 148bc4a51dSStefan Roese #address-cells = <2>; 158bc4a51dSStefan Roese #size-cells = <1>; 168bc4a51dSStefan Roese model = "amcc,canyonlands"; 178bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 18*71f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 198bc4a51dSStefan Roese 208bc4a51dSStefan Roese aliases { 218bc4a51dSStefan Roese ethernet0 = &EMAC0; 228bc4a51dSStefan Roese ethernet1 = &EMAC1; 238bc4a51dSStefan Roese serial0 = &UART0; 248bc4a51dSStefan Roese serial1 = &UART1; 258bc4a51dSStefan Roese }; 268bc4a51dSStefan Roese 278bc4a51dSStefan Roese cpus { 288bc4a51dSStefan Roese #address-cells = <1>; 298bc4a51dSStefan Roese #size-cells = <0>; 308bc4a51dSStefan Roese 318bc4a51dSStefan Roese cpu@0 { 328bc4a51dSStefan Roese device_type = "cpu"; 338bc4a51dSStefan Roese model = "PowerPC,460EX"; 34*71f34979SDavid Gibson reg = <0x00000000>; 358bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 368bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 37*71f34979SDavid Gibson i-cache-line-size = <32>; 38*71f34979SDavid Gibson d-cache-line-size = <32>; 39*71f34979SDavid Gibson i-cache-size = <32768>; 40*71f34979SDavid Gibson d-cache-size = <32768>; 418bc4a51dSStefan Roese dcr-controller; 428bc4a51dSStefan Roese dcr-access-method = "native"; 438bc4a51dSStefan Roese }; 448bc4a51dSStefan Roese }; 458bc4a51dSStefan Roese 468bc4a51dSStefan Roese memory { 478bc4a51dSStefan Roese device_type = "memory"; 48*71f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 498bc4a51dSStefan Roese }; 508bc4a51dSStefan Roese 518bc4a51dSStefan Roese UIC0: interrupt-controller0 { 528bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 538bc4a51dSStefan Roese interrupt-controller; 548bc4a51dSStefan Roese cell-index = <0>; 55*71f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 568bc4a51dSStefan Roese #address-cells = <0>; 578bc4a51dSStefan Roese #size-cells = <0>; 588bc4a51dSStefan Roese #interrupt-cells = <2>; 598bc4a51dSStefan Roese }; 608bc4a51dSStefan Roese 618bc4a51dSStefan Roese UIC1: interrupt-controller1 { 628bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 638bc4a51dSStefan Roese interrupt-controller; 648bc4a51dSStefan Roese cell-index = <1>; 65*71f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 668bc4a51dSStefan Roese #address-cells = <0>; 678bc4a51dSStefan Roese #size-cells = <0>; 688bc4a51dSStefan Roese #interrupt-cells = <2>; 69*71f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 708bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 718bc4a51dSStefan Roese }; 728bc4a51dSStefan Roese 738bc4a51dSStefan Roese UIC2: interrupt-controller2 { 748bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 758bc4a51dSStefan Roese interrupt-controller; 768bc4a51dSStefan Roese cell-index = <2>; 77*71f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 788bc4a51dSStefan Roese #address-cells = <0>; 798bc4a51dSStefan Roese #size-cells = <0>; 808bc4a51dSStefan Roese #interrupt-cells = <2>; 81*71f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 828bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 838bc4a51dSStefan Roese }; 848bc4a51dSStefan Roese 858bc4a51dSStefan Roese UIC3: interrupt-controller3 { 868bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 878bc4a51dSStefan Roese interrupt-controller; 888bc4a51dSStefan Roese cell-index = <3>; 89*71f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 908bc4a51dSStefan Roese #address-cells = <0>; 918bc4a51dSStefan Roese #size-cells = <0>; 928bc4a51dSStefan Roese #interrupt-cells = <2>; 93*71f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 948bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 958bc4a51dSStefan Roese }; 968bc4a51dSStefan Roese 978bc4a51dSStefan Roese SDR0: sdr { 988bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 99*71f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 1008bc4a51dSStefan Roese }; 1018bc4a51dSStefan Roese 1028bc4a51dSStefan Roese CPR0: cpr { 1038bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 104*71f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 1058bc4a51dSStefan Roese }; 1068bc4a51dSStefan Roese 1078bc4a51dSStefan Roese plb { 1088bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1098bc4a51dSStefan Roese #address-cells = <2>; 1108bc4a51dSStefan Roese #size-cells = <1>; 1118bc4a51dSStefan Roese ranges; 1128bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1138bc4a51dSStefan Roese 1148bc4a51dSStefan Roese SDRAM0: sdram { 1158bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 116*71f34979SDavid Gibson dcr-reg = <0x010 0x002>; 1178bc4a51dSStefan Roese }; 1188bc4a51dSStefan Roese 1198bc4a51dSStefan Roese MAL0: mcmal { 1208bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 121*71f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1228bc4a51dSStefan Roese num-tx-chans = <2>; 123*71f34979SDavid Gibson num-rx-chans = <16>; 1248bc4a51dSStefan Roese #address-cells = <0>; 1258bc4a51dSStefan Roese #size-cells = <0>; 1268bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 127*71f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 128*71f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 129*71f34979SDavid Gibson /*SERR*/ 0x3 0x4 130*71f34979SDavid Gibson /*TXDE*/ 0x4 0x4 131*71f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 1328bc4a51dSStefan Roese }; 1338bc4a51dSStefan Roese 1348bc4a51dSStefan Roese POB0: opb { 1358bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1368bc4a51dSStefan Roese #address-cells = <1>; 1378bc4a51dSStefan Roese #size-cells = <1>; 138*71f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 1398bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1408bc4a51dSStefan Roese 1418bc4a51dSStefan Roese EBC0: ebc { 1428bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 143*71f34979SDavid Gibson dcr-reg = <0x012 0x002>; 1448bc4a51dSStefan Roese #address-cells = <2>; 1458bc4a51dSStefan Roese #size-cells = <1>; 1468bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1475020231bSStefan Roese /* ranges property is supplied by U-Boot */ 148*71f34979SDavid Gibson interrupts = <0x6 0x4>; 1498bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1505020231bSStefan Roese 1515020231bSStefan Roese nor_flash@0,0 { 1525020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1535020231bSStefan Roese bank-width = <2>; 154*71f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 1555020231bSStefan Roese #address-cells = <1>; 1565020231bSStefan Roese #size-cells = <1>; 1575020231bSStefan Roese partition@0 { 1585020231bSStefan Roese label = "kernel"; 159*71f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 1605020231bSStefan Roese }; 1615020231bSStefan Roese partition@1e0000 { 1625020231bSStefan Roese label = "dtb"; 163*71f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 1645020231bSStefan Roese }; 1655020231bSStefan Roese partition@200000 { 1665020231bSStefan Roese label = "ramdisk"; 167*71f34979SDavid Gibson reg = <0x00200000 0x01400000>; 1685020231bSStefan Roese }; 1695020231bSStefan Roese partition@1600000 { 1705020231bSStefan Roese label = "jffs2"; 171*71f34979SDavid Gibson reg = <0x01600000 0x00400000>; 1725020231bSStefan Roese }; 1735020231bSStefan Roese partition@1a00000 { 1745020231bSStefan Roese label = "user"; 175*71f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 1765020231bSStefan Roese }; 1775020231bSStefan Roese partition@3f60000 { 1785020231bSStefan Roese label = "env"; 179*71f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 1805020231bSStefan Roese }; 1815020231bSStefan Roese partition@3fa0000 { 1825020231bSStefan Roese label = "u-boot"; 183*71f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 1845020231bSStefan Roese }; 1855020231bSStefan Roese }; 1868bc4a51dSStefan Roese }; 1878bc4a51dSStefan Roese 1888bc4a51dSStefan Roese UART0: serial@ef600300 { 1898bc4a51dSStefan Roese device_type = "serial"; 1908bc4a51dSStefan Roese compatible = "ns16550"; 191*71f34979SDavid Gibson reg = <0xef600300 0x00000008>; 192*71f34979SDavid Gibson virtual-reg = <0xef600300>; 1938bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1948bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1958bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 196*71f34979SDavid Gibson interrupts = <0x1 0x4>; 1978bc4a51dSStefan Roese }; 1988bc4a51dSStefan Roese 1998bc4a51dSStefan Roese UART1: serial@ef600400 { 2008bc4a51dSStefan Roese device_type = "serial"; 2018bc4a51dSStefan Roese compatible = "ns16550"; 202*71f34979SDavid Gibson reg = <0xef600400 0x00000008>; 203*71f34979SDavid Gibson virtual-reg = <0xef600400>; 2048bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2058bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2068bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 207*71f34979SDavid Gibson interrupts = <0x1 0x4>; 2088bc4a51dSStefan Roese }; 2098bc4a51dSStefan Roese 2108bc4a51dSStefan Roese UART2: serial@ef600500 { 2118bc4a51dSStefan Roese device_type = "serial"; 2128bc4a51dSStefan Roese compatible = "ns16550"; 213*71f34979SDavid Gibson reg = <0xef600500 0x00000008>; 214*71f34979SDavid Gibson virtual-reg = <0xef600500>; 2158bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2168bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2178bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 218*71f34979SDavid Gibson interrupts = <0x1d 0x4>; 2198bc4a51dSStefan Roese }; 2208bc4a51dSStefan Roese 2218bc4a51dSStefan Roese UART3: serial@ef600600 { 2228bc4a51dSStefan Roese device_type = "serial"; 2238bc4a51dSStefan Roese compatible = "ns16550"; 224*71f34979SDavid Gibson reg = <0xef600600 0x00000008>; 225*71f34979SDavid Gibson virtual-reg = <0xef600600>; 2268bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2278bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2288bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 229*71f34979SDavid Gibson interrupts = <0x1e 0x4>; 2308bc4a51dSStefan Roese }; 2318bc4a51dSStefan Roese 2328bc4a51dSStefan Roese IIC0: i2c@ef600700 { 2338bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 234*71f34979SDavid Gibson reg = <0xef600700 0x00000014>; 2358bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 236*71f34979SDavid Gibson interrupts = <0x2 0x4>; 2378bc4a51dSStefan Roese }; 2388bc4a51dSStefan Roese 2398bc4a51dSStefan Roese IIC1: i2c@ef600800 { 2408bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 241*71f34979SDavid Gibson reg = <0xef600800 0x00000014>; 2428bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 243*71f34979SDavid Gibson interrupts = <0x3 0x4>; 2448bc4a51dSStefan Roese }; 2458bc4a51dSStefan Roese 2468bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 2478bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 248*71f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 2498bc4a51dSStefan Roese }; 2508bc4a51dSStefan Roese 2518bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 2528bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 253*71f34979SDavid Gibson reg = <0xef601500 0x00000008>; 2548bc4a51dSStefan Roese has-mdio; 2558bc4a51dSStefan Roese }; 2568bc4a51dSStefan Roese 257a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 258a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 259*71f34979SDavid Gibson reg = <0xef601350 0x00000030>; 260a6190a84SStefan Roese }; 261a6190a84SStefan Roese 262a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 263a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 264*71f34979SDavid Gibson reg = <0xef601450 0x00000030>; 265a6190a84SStefan Roese }; 266a6190a84SStefan Roese 2678bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 2688bc4a51dSStefan Roese device_type = "network"; 2698bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2708bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 271*71f34979SDavid Gibson interrupts = <0x0 0x1>; 2728bc4a51dSStefan Roese #interrupt-cells = <1>; 2738bc4a51dSStefan Roese #address-cells = <0>; 2748bc4a51dSStefan Roese #size-cells = <0>; 275*71f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 276*71f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 277*71f34979SDavid Gibson reg = <0xef600e00 0x00000070>; 2788bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2798bc4a51dSStefan Roese mal-device = <&MAL0>; 2808bc4a51dSStefan Roese mal-tx-channel = <0>; 2818bc4a51dSStefan Roese mal-rx-channel = <0>; 2828bc4a51dSStefan Roese cell-index = <0>; 283*71f34979SDavid Gibson max-frame-size = <9000>; 284*71f34979SDavid Gibson rx-fifo-size = <4096>; 285*71f34979SDavid Gibson tx-fifo-size = <2048>; 2868bc4a51dSStefan Roese phy-mode = "rgmii"; 287*71f34979SDavid Gibson phy-map = <0x00000000>; 2888bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 2898bc4a51dSStefan Roese rgmii-channel = <0>; 290a6190a84SStefan Roese tah-device = <&TAH0>; 291a6190a84SStefan Roese tah-channel = <0>; 2928bc4a51dSStefan Roese has-inverted-stacr-oc; 2938bc4a51dSStefan Roese has-new-stacr-staopc; 2948bc4a51dSStefan Roese }; 2958bc4a51dSStefan Roese 2968bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 2978bc4a51dSStefan Roese device_type = "network"; 2988bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2998bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 300*71f34979SDavid Gibson interrupts = <0x0 0x1>; 3018bc4a51dSStefan Roese #interrupt-cells = <1>; 3028bc4a51dSStefan Roese #address-cells = <0>; 3038bc4a51dSStefan Roese #size-cells = <0>; 304*71f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 305*71f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 306*71f34979SDavid Gibson reg = <0xef600f00 0x00000070>; 3078bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3088bc4a51dSStefan Roese mal-device = <&MAL0>; 3098bc4a51dSStefan Roese mal-tx-channel = <1>; 3108bc4a51dSStefan Roese mal-rx-channel = <8>; 3118bc4a51dSStefan Roese cell-index = <1>; 312*71f34979SDavid Gibson max-frame-size = <9000>; 313*71f34979SDavid Gibson rx-fifo-size = <4096>; 314*71f34979SDavid Gibson tx-fifo-size = <2048>; 3158bc4a51dSStefan Roese phy-mode = "rgmii"; 316*71f34979SDavid Gibson phy-map = <0x00000000>; 3178bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3188bc4a51dSStefan Roese rgmii-channel = <1>; 319a6190a84SStefan Roese tah-device = <&TAH1>; 320a6190a84SStefan Roese tah-channel = <1>; 3218bc4a51dSStefan Roese has-inverted-stacr-oc; 3228bc4a51dSStefan Roese has-new-stacr-staopc; 323a6190a84SStefan Roese mdio-device = <&EMAC0>; 3248bc4a51dSStefan Roese }; 3258bc4a51dSStefan Roese }; 3268bc4a51dSStefan Roese 3278bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 3288bc4a51dSStefan Roese device_type = "pci"; 3298bc4a51dSStefan Roese #interrupt-cells = <1>; 3308bc4a51dSStefan Roese #size-cells = <2>; 3318bc4a51dSStefan Roese #address-cells = <3>; 3328bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 3338bc4a51dSStefan Roese primary; 3348bc4a51dSStefan Roese large-inbound-windows; 3358bc4a51dSStefan Roese enable-msi-hole; 336*71f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 337*71f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 338*71f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 339*71f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 340*71f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 3418bc4a51dSStefan Roese 3428bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3438bc4a51dSStefan Roese * later cannot be changed 3448bc4a51dSStefan Roese */ 345*71f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 346*71f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 3478bc4a51dSStefan Roese 3488bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 349*71f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 3508bc4a51dSStefan Roese 3518bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 352*71f34979SDavid Gibson bus-range = <0x0 0x3f>; 3538bc4a51dSStefan Roese 3548bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 355*71f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 356*71f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 3578bc4a51dSStefan Roese }; 3588bc4a51dSStefan Roese 3598bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 3608bc4a51dSStefan Roese device_type = "pci"; 3618bc4a51dSStefan Roese #interrupt-cells = <1>; 3628bc4a51dSStefan Roese #size-cells = <2>; 3638bc4a51dSStefan Roese #address-cells = <3>; 3648bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 3658bc4a51dSStefan Roese primary; 366*71f34979SDavid Gibson port = <0x0>; /* port number */ 367*71f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 368*71f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 369*71f34979SDavid Gibson dcr-reg = <0x100 0x020>; 370*71f34979SDavid Gibson sdr-base = <0x300>; 3718bc4a51dSStefan Roese 3728bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3738bc4a51dSStefan Roese * later cannot be changed 3748bc4a51dSStefan Roese */ 375*71f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 376*71f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 3778bc4a51dSStefan Roese 3788bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 379*71f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 3808bc4a51dSStefan Roese 3818bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 382*71f34979SDavid Gibson bus-range = <0x40 0x7f>; 3838bc4a51dSStefan Roese 3848bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3858bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 3868bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 3878bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 3888bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3898bc4a51dSStefan Roese * below are basically de-swizzled numbers. 3908bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3918bc4a51dSStefan Roese */ 392*71f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 3938bc4a51dSStefan Roese interrupt-map = < 394*71f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 395*71f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 396*71f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 397*71f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 3988bc4a51dSStefan Roese }; 3998bc4a51dSStefan Roese 4008bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 4018bc4a51dSStefan Roese device_type = "pci"; 4028bc4a51dSStefan Roese #interrupt-cells = <1>; 4038bc4a51dSStefan Roese #size-cells = <2>; 4048bc4a51dSStefan Roese #address-cells = <3>; 4058bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4068bc4a51dSStefan Roese primary; 407*71f34979SDavid Gibson port = <0x1>; /* port number */ 408*71f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 409*71f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 410*71f34979SDavid Gibson dcr-reg = <0x120 0x020>; 411*71f34979SDavid Gibson sdr-base = <0x340>; 4128bc4a51dSStefan Roese 4138bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4148bc4a51dSStefan Roese * later cannot be changed 4158bc4a51dSStefan Roese */ 416*71f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 417*71f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 4188bc4a51dSStefan Roese 4198bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 420*71f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4218bc4a51dSStefan Roese 4228bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 423*71f34979SDavid Gibson bus-range = <0x80 0xbf>; 4248bc4a51dSStefan Roese 4258bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4268bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4278bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4288bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4298bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4308bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4318bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4328bc4a51dSStefan Roese */ 433*71f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4348bc4a51dSStefan Roese interrupt-map = < 435*71f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 436*71f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 437*71f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 438*71f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 4398bc4a51dSStefan Roese }; 4408bc4a51dSStefan Roese }; 4418bc4a51dSStefan Roese}; 442