18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 48bc4a51dSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 118bc4a51dSStefan Roese/ { 128bc4a51dSStefan Roese #address-cells = <2>; 138bc4a51dSStefan Roese #size-cells = <1>; 148bc4a51dSStefan Roese model = "amcc,canyonlands"; 158bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 168bc4a51dSStefan Roese dcr-parent = <&/cpus/cpu@0>; 178bc4a51dSStefan Roese 188bc4a51dSStefan Roese aliases { 198bc4a51dSStefan Roese ethernet0 = &EMAC0; 208bc4a51dSStefan Roese ethernet1 = &EMAC1; 218bc4a51dSStefan Roese serial0 = &UART0; 228bc4a51dSStefan Roese serial1 = &UART1; 238bc4a51dSStefan Roese }; 248bc4a51dSStefan Roese 258bc4a51dSStefan Roese cpus { 268bc4a51dSStefan Roese #address-cells = <1>; 278bc4a51dSStefan Roese #size-cells = <0>; 288bc4a51dSStefan Roese 298bc4a51dSStefan Roese cpu@0 { 308bc4a51dSStefan Roese device_type = "cpu"; 318bc4a51dSStefan Roese model = "PowerPC,460EX"; 328bc4a51dSStefan Roese reg = <0>; 338bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 348bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 358bc4a51dSStefan Roese i-cache-line-size = <20>; 368bc4a51dSStefan Roese d-cache-line-size = <20>; 378bc4a51dSStefan Roese i-cache-size = <8000>; 388bc4a51dSStefan Roese d-cache-size = <8000>; 398bc4a51dSStefan Roese dcr-controller; 408bc4a51dSStefan Roese dcr-access-method = "native"; 418bc4a51dSStefan Roese }; 428bc4a51dSStefan Roese }; 438bc4a51dSStefan Roese 448bc4a51dSStefan Roese memory { 458bc4a51dSStefan Roese device_type = "memory"; 468bc4a51dSStefan Roese reg = <0 0 0>; /* Filled in by U-Boot */ 478bc4a51dSStefan Roese }; 488bc4a51dSStefan Roese 498bc4a51dSStefan Roese UIC0: interrupt-controller0 { 508bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 518bc4a51dSStefan Roese interrupt-controller; 528bc4a51dSStefan Roese cell-index = <0>; 538bc4a51dSStefan Roese dcr-reg = <0c0 009>; 548bc4a51dSStefan Roese #address-cells = <0>; 558bc4a51dSStefan Roese #size-cells = <0>; 568bc4a51dSStefan Roese #interrupt-cells = <2>; 578bc4a51dSStefan Roese }; 588bc4a51dSStefan Roese 598bc4a51dSStefan Roese UIC1: interrupt-controller1 { 608bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 618bc4a51dSStefan Roese interrupt-controller; 628bc4a51dSStefan Roese cell-index = <1>; 638bc4a51dSStefan Roese dcr-reg = <0d0 009>; 648bc4a51dSStefan Roese #address-cells = <0>; 658bc4a51dSStefan Roese #size-cells = <0>; 668bc4a51dSStefan Roese #interrupt-cells = <2>; 678bc4a51dSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 688bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 698bc4a51dSStefan Roese }; 708bc4a51dSStefan Roese 718bc4a51dSStefan Roese UIC2: interrupt-controller2 { 728bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 738bc4a51dSStefan Roese interrupt-controller; 748bc4a51dSStefan Roese cell-index = <2>; 758bc4a51dSStefan Roese dcr-reg = <0e0 009>; 768bc4a51dSStefan Roese #address-cells = <0>; 778bc4a51dSStefan Roese #size-cells = <0>; 788bc4a51dSStefan Roese #interrupt-cells = <2>; 798bc4a51dSStefan Roese interrupts = <a 4 b 4>; /* cascade */ 808bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 818bc4a51dSStefan Roese }; 828bc4a51dSStefan Roese 838bc4a51dSStefan Roese UIC3: interrupt-controller3 { 848bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 858bc4a51dSStefan Roese interrupt-controller; 868bc4a51dSStefan Roese cell-index = <3>; 878bc4a51dSStefan Roese dcr-reg = <0f0 009>; 888bc4a51dSStefan Roese #address-cells = <0>; 898bc4a51dSStefan Roese #size-cells = <0>; 908bc4a51dSStefan Roese #interrupt-cells = <2>; 918bc4a51dSStefan Roese interrupts = <10 4 11 4>; /* cascade */ 928bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 938bc4a51dSStefan Roese }; 948bc4a51dSStefan Roese 958bc4a51dSStefan Roese SDR0: sdr { 968bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 978bc4a51dSStefan Roese dcr-reg = <00e 002>; 988bc4a51dSStefan Roese }; 998bc4a51dSStefan Roese 1008bc4a51dSStefan Roese CPR0: cpr { 1018bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 1028bc4a51dSStefan Roese dcr-reg = <00c 002>; 1038bc4a51dSStefan Roese }; 1048bc4a51dSStefan Roese 1058bc4a51dSStefan Roese plb { 1068bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1078bc4a51dSStefan Roese #address-cells = <2>; 1088bc4a51dSStefan Roese #size-cells = <1>; 1098bc4a51dSStefan Roese ranges; 1108bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1118bc4a51dSStefan Roese 1128bc4a51dSStefan Roese SDRAM0: sdram { 1138bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 1148bc4a51dSStefan Roese dcr-reg = <010 2>; 1158bc4a51dSStefan Roese }; 1168bc4a51dSStefan Roese 1178bc4a51dSStefan Roese MAL0: mcmal { 1188bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 1198bc4a51dSStefan Roese dcr-reg = <180 62>; 1208bc4a51dSStefan Roese num-tx-chans = <2>; 1218bc4a51dSStefan Roese num-rx-chans = <10>; 1228bc4a51dSStefan Roese #address-cells = <0>; 1238bc4a51dSStefan Roese #size-cells = <0>; 1248bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 1258bc4a51dSStefan Roese interrupts = < /*TXEOB*/ 6 4 1268bc4a51dSStefan Roese /*RXEOB*/ 7 4 1278bc4a51dSStefan Roese /*SERR*/ 3 4 1288bc4a51dSStefan Roese /*TXDE*/ 4 4 1298bc4a51dSStefan Roese /*RXDE*/ 5 4>; 1308bc4a51dSStefan Roese }; 1318bc4a51dSStefan Roese 1328bc4a51dSStefan Roese POB0: opb { 1338bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1348bc4a51dSStefan Roese #address-cells = <1>; 1358bc4a51dSStefan Roese #size-cells = <1>; 1368bc4a51dSStefan Roese ranges = <b0000000 4 b0000000 50000000>; 1378bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1388bc4a51dSStefan Roese 1398bc4a51dSStefan Roese EBC0: ebc { 1408bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 1418bc4a51dSStefan Roese dcr-reg = <012 2>; 1428bc4a51dSStefan Roese #address-cells = <2>; 1438bc4a51dSStefan Roese #size-cells = <1>; 1448bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 145*5020231bSStefan Roese /* ranges property is supplied by U-Boot */ 1468bc4a51dSStefan Roese interrupts = <6 4>; 1478bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 148*5020231bSStefan Roese 149*5020231bSStefan Roese nor_flash@0,0 { 150*5020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 151*5020231bSStefan Roese bank-width = <2>; 152*5020231bSStefan Roese reg = <0 000000 4000000>; 153*5020231bSStefan Roese #address-cells = <1>; 154*5020231bSStefan Roese #size-cells = <1>; 155*5020231bSStefan Roese partition@0 { 156*5020231bSStefan Roese label = "kernel"; 157*5020231bSStefan Roese reg = <0 1e0000>; 158*5020231bSStefan Roese }; 159*5020231bSStefan Roese partition@1e0000 { 160*5020231bSStefan Roese label = "dtb"; 161*5020231bSStefan Roese reg = <1e0000 20000>; 162*5020231bSStefan Roese }; 163*5020231bSStefan Roese partition@200000 { 164*5020231bSStefan Roese label = "ramdisk"; 165*5020231bSStefan Roese reg = <200000 1400000>; 166*5020231bSStefan Roese }; 167*5020231bSStefan Roese partition@1600000 { 168*5020231bSStefan Roese label = "jffs2"; 169*5020231bSStefan Roese reg = <1600000 400000>; 170*5020231bSStefan Roese }; 171*5020231bSStefan Roese partition@1a00000 { 172*5020231bSStefan Roese label = "user"; 173*5020231bSStefan Roese reg = <1a00000 2560000>; 174*5020231bSStefan Roese }; 175*5020231bSStefan Roese partition@3f60000 { 176*5020231bSStefan Roese label = "env"; 177*5020231bSStefan Roese reg = <3f60000 40000>; 178*5020231bSStefan Roese }; 179*5020231bSStefan Roese partition@3fa0000 { 180*5020231bSStefan Roese label = "u-boot"; 181*5020231bSStefan Roese reg = <3fa0000 60000>; 182*5020231bSStefan Roese }; 183*5020231bSStefan Roese }; 1848bc4a51dSStefan Roese }; 1858bc4a51dSStefan Roese 1868bc4a51dSStefan Roese UART0: serial@ef600300 { 1878bc4a51dSStefan Roese device_type = "serial"; 1888bc4a51dSStefan Roese compatible = "ns16550"; 1898bc4a51dSStefan Roese reg = <ef600300 8>; 1908bc4a51dSStefan Roese virtual-reg = <ef600300>; 1918bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1928bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 1938bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1948bc4a51dSStefan Roese interrupts = <1 4>; 1958bc4a51dSStefan Roese }; 1968bc4a51dSStefan Roese 1978bc4a51dSStefan Roese UART1: serial@ef600400 { 1988bc4a51dSStefan Roese device_type = "serial"; 1998bc4a51dSStefan Roese compatible = "ns16550"; 2008bc4a51dSStefan Roese reg = <ef600400 8>; 2018bc4a51dSStefan Roese virtual-reg = <ef600400>; 2028bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2038bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2048bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 2058bc4a51dSStefan Roese interrupts = <1 4>; 2068bc4a51dSStefan Roese }; 2078bc4a51dSStefan Roese 2088bc4a51dSStefan Roese UART2: serial@ef600500 { 2098bc4a51dSStefan Roese device_type = "serial"; 2108bc4a51dSStefan Roese compatible = "ns16550"; 2118bc4a51dSStefan Roese reg = <ef600500 8>; 2128bc4a51dSStefan Roese virtual-reg = <ef600500>; 2138bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2148bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2158bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 2168bc4a51dSStefan Roese interrupts = <1d 4>; 2178bc4a51dSStefan Roese }; 2188bc4a51dSStefan Roese 2198bc4a51dSStefan Roese UART3: serial@ef600600 { 2208bc4a51dSStefan Roese device_type = "serial"; 2218bc4a51dSStefan Roese compatible = "ns16550"; 2228bc4a51dSStefan Roese reg = <ef600600 8>; 2238bc4a51dSStefan Roese virtual-reg = <ef600600>; 2248bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2258bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2268bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 2278bc4a51dSStefan Roese interrupts = <1e 4>; 2288bc4a51dSStefan Roese }; 2298bc4a51dSStefan Roese 2308bc4a51dSStefan Roese IIC0: i2c@ef600700 { 2318bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 2328bc4a51dSStefan Roese reg = <ef600700 14>; 2338bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 2348bc4a51dSStefan Roese interrupts = <2 4>; 2358bc4a51dSStefan Roese }; 2368bc4a51dSStefan Roese 2378bc4a51dSStefan Roese IIC1: i2c@ef600800 { 2388bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 2398bc4a51dSStefan Roese reg = <ef600800 14>; 2408bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 2418bc4a51dSStefan Roese interrupts = <3 4>; 2428bc4a51dSStefan Roese }; 2438bc4a51dSStefan Roese 2448bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 2458bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 2468bc4a51dSStefan Roese reg = <ef600d00 c>; 2478bc4a51dSStefan Roese }; 2488bc4a51dSStefan Roese 2498bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 2508bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 2518bc4a51dSStefan Roese reg = <ef601500 8>; 2528bc4a51dSStefan Roese has-mdio; 2538bc4a51dSStefan Roese }; 2548bc4a51dSStefan Roese 255a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 256a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 257a6190a84SStefan Roese reg = <ef601350 30>; 258a6190a84SStefan Roese }; 259a6190a84SStefan Roese 260a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 261a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 262a6190a84SStefan Roese reg = <ef601450 30>; 263a6190a84SStefan Roese }; 264a6190a84SStefan Roese 2658bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 2668bc4a51dSStefan Roese device_type = "network"; 2678bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2688bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 2698bc4a51dSStefan Roese interrupts = <0 1>; 2708bc4a51dSStefan Roese #interrupt-cells = <1>; 2718bc4a51dSStefan Roese #address-cells = <0>; 2728bc4a51dSStefan Roese #size-cells = <0>; 2738bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 10 4 2748bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 14 4>; 2758bc4a51dSStefan Roese reg = <ef600e00 70>; 2768bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2778bc4a51dSStefan Roese mal-device = <&MAL0>; 2788bc4a51dSStefan Roese mal-tx-channel = <0>; 2798bc4a51dSStefan Roese mal-rx-channel = <0>; 2808bc4a51dSStefan Roese cell-index = <0>; 2818bc4a51dSStefan Roese max-frame-size = <2328>; 2828bc4a51dSStefan Roese rx-fifo-size = <1000>; 2838bc4a51dSStefan Roese tx-fifo-size = <800>; 2848bc4a51dSStefan Roese phy-mode = "rgmii"; 2858bc4a51dSStefan Roese phy-map = <00000000>; 2868bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 2878bc4a51dSStefan Roese rgmii-channel = <0>; 288a6190a84SStefan Roese tah-device = <&TAH0>; 289a6190a84SStefan Roese tah-channel = <0>; 2908bc4a51dSStefan Roese has-inverted-stacr-oc; 2918bc4a51dSStefan Roese has-new-stacr-staopc; 2928bc4a51dSStefan Roese }; 2938bc4a51dSStefan Roese 2948bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 2958bc4a51dSStefan Roese device_type = "network"; 2968bc4a51dSStefan Roese compatible = "ibm,emac-460ex", "ibm,emac4"; 2978bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 2988bc4a51dSStefan Roese interrupts = <0 1>; 2998bc4a51dSStefan Roese #interrupt-cells = <1>; 3008bc4a51dSStefan Roese #address-cells = <0>; 3018bc4a51dSStefan Roese #size-cells = <0>; 3028bc4a51dSStefan Roese interrupt-map = </*Status*/ 0 &UIC2 11 4 3038bc4a51dSStefan Roese /*Wake*/ 1 &UIC2 15 4>; 3048bc4a51dSStefan Roese reg = <ef600f00 70>; 3058bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3068bc4a51dSStefan Roese mal-device = <&MAL0>; 3078bc4a51dSStefan Roese mal-tx-channel = <1>; 3088bc4a51dSStefan Roese mal-rx-channel = <8>; 3098bc4a51dSStefan Roese cell-index = <1>; 3108bc4a51dSStefan Roese max-frame-size = <2328>; 3118bc4a51dSStefan Roese rx-fifo-size = <1000>; 3128bc4a51dSStefan Roese tx-fifo-size = <800>; 3138bc4a51dSStefan Roese phy-mode = "rgmii"; 3148bc4a51dSStefan Roese phy-map = <00000000>; 3158bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3168bc4a51dSStefan Roese rgmii-channel = <1>; 317a6190a84SStefan Roese tah-device = <&TAH1>; 318a6190a84SStefan Roese tah-channel = <1>; 3198bc4a51dSStefan Roese has-inverted-stacr-oc; 3208bc4a51dSStefan Roese has-new-stacr-staopc; 321a6190a84SStefan Roese mdio-device = <&EMAC0>; 3228bc4a51dSStefan Roese }; 3238bc4a51dSStefan Roese }; 3248bc4a51dSStefan Roese 3258bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 3268bc4a51dSStefan Roese device_type = "pci"; 3278bc4a51dSStefan Roese #interrupt-cells = <1>; 3288bc4a51dSStefan Roese #size-cells = <2>; 3298bc4a51dSStefan Roese #address-cells = <3>; 3308bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 3318bc4a51dSStefan Roese primary; 3328bc4a51dSStefan Roese large-inbound-windows; 3338bc4a51dSStefan Roese enable-msi-hole; 3348bc4a51dSStefan Roese reg = <c 0ec00000 8 /* Config space access */ 3358bc4a51dSStefan Roese 0 0 0 /* no IACK cycles */ 3368bc4a51dSStefan Roese c 0ed00000 4 /* Special cycles */ 3378bc4a51dSStefan Roese c 0ec80000 100 /* Internal registers */ 3388bc4a51dSStefan Roese c 0ec80100 fc>; /* Internal messaging registers */ 3398bc4a51dSStefan Roese 3408bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3418bc4a51dSStefan Roese * later cannot be changed 3428bc4a51dSStefan Roese */ 3438bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 3448bc4a51dSStefan Roese 01000000 0 00000000 0000000c 08000000 0 00010000>; 3458bc4a51dSStefan Roese 3468bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 3478bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 3488bc4a51dSStefan Roese 3498bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 3508bc4a51dSStefan Roese bus-range = <0 3f>; 3518bc4a51dSStefan Roese 3528bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 3538bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 0>; 3548bc4a51dSStefan Roese interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 3558bc4a51dSStefan Roese }; 3568bc4a51dSStefan Roese 3578bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 3588bc4a51dSStefan Roese device_type = "pci"; 3598bc4a51dSStefan Roese #interrupt-cells = <1>; 3608bc4a51dSStefan Roese #size-cells = <2>; 3618bc4a51dSStefan Roese #address-cells = <3>; 3628bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 3638bc4a51dSStefan Roese primary; 3648bc4a51dSStefan Roese port = <0>; /* port number */ 3658bc4a51dSStefan Roese reg = <d 00000000 20000000 /* Config space access */ 3668bc4a51dSStefan Roese c 08010000 00001000>; /* Registers */ 3678bc4a51dSStefan Roese dcr-reg = <100 020>; 3688bc4a51dSStefan Roese sdr-base = <300>; 3698bc4a51dSStefan Roese 3708bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3718bc4a51dSStefan Roese * later cannot be changed 3728bc4a51dSStefan Roese */ 3738bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 3748bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80000000 0 00010000>; 3758bc4a51dSStefan Roese 3768bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 3778bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 3788bc4a51dSStefan Roese 3798bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 3808bc4a51dSStefan Roese bus-range = <40 7f>; 3818bc4a51dSStefan Roese 3828bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 3838bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 3848bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 3858bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 3868bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 3878bc4a51dSStefan Roese * below are basically de-swizzled numbers. 3888bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 3898bc4a51dSStefan Roese */ 3908bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 3918bc4a51dSStefan Roese interrupt-map = < 3928bc4a51dSStefan Roese 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 3938bc4a51dSStefan Roese 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 3948bc4a51dSStefan Roese 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 3958bc4a51dSStefan Roese 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 3968bc4a51dSStefan Roese }; 3978bc4a51dSStefan Roese 3988bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 3998bc4a51dSStefan Roese device_type = "pci"; 4008bc4a51dSStefan Roese #interrupt-cells = <1>; 4018bc4a51dSStefan Roese #size-cells = <2>; 4028bc4a51dSStefan Roese #address-cells = <3>; 4038bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4048bc4a51dSStefan Roese primary; 4058bc4a51dSStefan Roese port = <1>; /* port number */ 4068bc4a51dSStefan Roese reg = <d 20000000 20000000 /* Config space access */ 4078bc4a51dSStefan Roese c 08011000 00001000>; /* Registers */ 4088bc4a51dSStefan Roese dcr-reg = <120 020>; 4098bc4a51dSStefan Roese sdr-base = <340>; 4108bc4a51dSStefan Roese 4118bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4128bc4a51dSStefan Roese * later cannot be changed 4138bc4a51dSStefan Roese */ 4148bc4a51dSStefan Roese ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 4158bc4a51dSStefan Roese 01000000 0 00000000 0000000f 80010000 0 00010000>; 4168bc4a51dSStefan Roese 4178bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 4188bc4a51dSStefan Roese dma-ranges = <42000000 0 0 0 0 0 80000000>; 4198bc4a51dSStefan Roese 4208bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 4218bc4a51dSStefan Roese bus-range = <80 bf>; 4228bc4a51dSStefan Roese 4238bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4248bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4258bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4268bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4278bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4288bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4298bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4308bc4a51dSStefan Roese */ 4318bc4a51dSStefan Roese interrupt-map-mask = <0000 0 0 7>; 4328bc4a51dSStefan Roese interrupt-map = < 4338bc4a51dSStefan Roese 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 4348bc4a51dSStefan Roese 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 4358bc4a51dSStefan Roese 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 4368bc4a51dSStefan Roese 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 4378bc4a51dSStefan Roese }; 4388bc4a51dSStefan Roese }; 4398bc4a51dSStefan Roese}; 440