18bc4a51dSStefan Roese/* 28bc4a51dSStefan Roese * Device Tree Source for AMCC Canyonlands (460EX) 38bc4a51dSStefan Roese * 48bc4a51dSStefan Roese * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 58bc4a51dSStefan Roese * 68bc4a51dSStefan Roese * This file is licensed under the terms of the GNU General Public 78bc4a51dSStefan Roese * License version 2. This program is licensed "as is" without 88bc4a51dSStefan Roese * any warranty of any kind, whether express or implied. 98bc4a51dSStefan Roese */ 108bc4a51dSStefan Roese 1171f34979SDavid Gibson/dts-v1/; 1271f34979SDavid Gibson 138bc4a51dSStefan Roese/ { 148bc4a51dSStefan Roese #address-cells = <2>; 158bc4a51dSStefan Roese #size-cells = <1>; 168bc4a51dSStefan Roese model = "amcc,canyonlands"; 178bc4a51dSStefan Roese compatible = "amcc,canyonlands"; 1871f34979SDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 198bc4a51dSStefan Roese 208bc4a51dSStefan Roese aliases { 218bc4a51dSStefan Roese ethernet0 = &EMAC0; 228bc4a51dSStefan Roese ethernet1 = &EMAC1; 238bc4a51dSStefan Roese serial0 = &UART0; 248bc4a51dSStefan Roese serial1 = &UART1; 258bc4a51dSStefan Roese }; 268bc4a51dSStefan Roese 278bc4a51dSStefan Roese cpus { 288bc4a51dSStefan Roese #address-cells = <1>; 298bc4a51dSStefan Roese #size-cells = <0>; 308bc4a51dSStefan Roese 318bc4a51dSStefan Roese cpu@0 { 328bc4a51dSStefan Roese device_type = "cpu"; 338bc4a51dSStefan Roese model = "PowerPC,460EX"; 3471f34979SDavid Gibson reg = <0x00000000>; 358bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 368bc4a51dSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f34979SDavid Gibson i-cache-line-size = <32>; 3871f34979SDavid Gibson d-cache-line-size = <32>; 3971f34979SDavid Gibson i-cache-size = <32768>; 4071f34979SDavid Gibson d-cache-size = <32768>; 418bc4a51dSStefan Roese dcr-controller; 428bc4a51dSStefan Roese dcr-access-method = "native"; 43cd85400aSStefan Roese next-level-cache = <&L2C0>; 448bc4a51dSStefan Roese }; 458bc4a51dSStefan Roese }; 468bc4a51dSStefan Roese 478bc4a51dSStefan Roese memory { 488bc4a51dSStefan Roese device_type = "memory"; 4971f34979SDavid Gibson reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ 508bc4a51dSStefan Roese }; 518bc4a51dSStefan Roese 528bc4a51dSStefan Roese UIC0: interrupt-controller0 { 538bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 548bc4a51dSStefan Roese interrupt-controller; 558bc4a51dSStefan Roese cell-index = <0>; 5671f34979SDavid Gibson dcr-reg = <0x0c0 0x009>; 578bc4a51dSStefan Roese #address-cells = <0>; 588bc4a51dSStefan Roese #size-cells = <0>; 598bc4a51dSStefan Roese #interrupt-cells = <2>; 608bc4a51dSStefan Roese }; 618bc4a51dSStefan Roese 628bc4a51dSStefan Roese UIC1: interrupt-controller1 { 638bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 648bc4a51dSStefan Roese interrupt-controller; 658bc4a51dSStefan Roese cell-index = <1>; 6671f34979SDavid Gibson dcr-reg = <0x0d0 0x009>; 678bc4a51dSStefan Roese #address-cells = <0>; 688bc4a51dSStefan Roese #size-cells = <0>; 698bc4a51dSStefan Roese #interrupt-cells = <2>; 7071f34979SDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 718bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 728bc4a51dSStefan Roese }; 738bc4a51dSStefan Roese 748bc4a51dSStefan Roese UIC2: interrupt-controller2 { 758bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 768bc4a51dSStefan Roese interrupt-controller; 778bc4a51dSStefan Roese cell-index = <2>; 7871f34979SDavid Gibson dcr-reg = <0x0e0 0x009>; 798bc4a51dSStefan Roese #address-cells = <0>; 808bc4a51dSStefan Roese #size-cells = <0>; 818bc4a51dSStefan Roese #interrupt-cells = <2>; 8271f34979SDavid Gibson interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ 838bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 848bc4a51dSStefan Roese }; 858bc4a51dSStefan Roese 868bc4a51dSStefan Roese UIC3: interrupt-controller3 { 878bc4a51dSStefan Roese compatible = "ibm,uic-460ex","ibm,uic"; 888bc4a51dSStefan Roese interrupt-controller; 898bc4a51dSStefan Roese cell-index = <3>; 9071f34979SDavid Gibson dcr-reg = <0x0f0 0x009>; 918bc4a51dSStefan Roese #address-cells = <0>; 928bc4a51dSStefan Roese #size-cells = <0>; 938bc4a51dSStefan Roese #interrupt-cells = <2>; 9471f34979SDavid Gibson interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ 958bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 968bc4a51dSStefan Roese }; 978bc4a51dSStefan Roese 988bc4a51dSStefan Roese SDR0: sdr { 998bc4a51dSStefan Roese compatible = "ibm,sdr-460ex"; 10071f34979SDavid Gibson dcr-reg = <0x00e 0x002>; 1018bc4a51dSStefan Roese }; 1028bc4a51dSStefan Roese 1038bc4a51dSStefan Roese CPR0: cpr { 1048bc4a51dSStefan Roese compatible = "ibm,cpr-460ex"; 10571f34979SDavid Gibson dcr-reg = <0x00c 0x002>; 1068bc4a51dSStefan Roese }; 1078bc4a51dSStefan Roese 108cd85400aSStefan Roese L2C0: l2c { 109cd85400aSStefan Roese compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; 110cd85400aSStefan Roese dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 111cd85400aSStefan Roese 0x030 0x008>; /* L2 cache DCR's */ 112cd85400aSStefan Roese cache-line-size = <32>; /* 32 bytes */ 113cd85400aSStefan Roese cache-size = <262144>; /* L2, 256K */ 114cd85400aSStefan Roese interrupt-parent = <&UIC1>; 115cd85400aSStefan Roese interrupts = <11 1>; 116cd85400aSStefan Roese }; 117cd85400aSStefan Roese 1188bc4a51dSStefan Roese plb { 1198bc4a51dSStefan Roese compatible = "ibm,plb-460ex", "ibm,plb4"; 1208bc4a51dSStefan Roese #address-cells = <2>; 1218bc4a51dSStefan Roese #size-cells = <1>; 1228bc4a51dSStefan Roese ranges; 1238bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1248bc4a51dSStefan Roese 1258bc4a51dSStefan Roese SDRAM0: sdram { 1268bc4a51dSStefan Roese compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 12771f34979SDavid Gibson dcr-reg = <0x010 0x002>; 1288bc4a51dSStefan Roese }; 1298bc4a51dSStefan Roese 130*049359d6SJames Hsiao CRYPTO: crypto@180000 { 131*049359d6SJames Hsiao compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; 132*049359d6SJames Hsiao reg = <4 0x00180000 0x80400>; 133*049359d6SJames Hsiao interrupt-parent = <&UIC0>; 134*049359d6SJames Hsiao interrupts = <0x1d 0x4>; 135*049359d6SJames Hsiao }; 136*049359d6SJames Hsiao 1378bc4a51dSStefan Roese MAL0: mcmal { 1388bc4a51dSStefan Roese compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 13971f34979SDavid Gibson dcr-reg = <0x180 0x062>; 1408bc4a51dSStefan Roese num-tx-chans = <2>; 14171f34979SDavid Gibson num-rx-chans = <16>; 1428bc4a51dSStefan Roese #address-cells = <0>; 1438bc4a51dSStefan Roese #size-cells = <0>; 1448bc4a51dSStefan Roese interrupt-parent = <&UIC2>; 14571f34979SDavid Gibson interrupts = < /*TXEOB*/ 0x6 0x4 14671f34979SDavid Gibson /*RXEOB*/ 0x7 0x4 14771f34979SDavid Gibson /*SERR*/ 0x3 0x4 14871f34979SDavid Gibson /*TXDE*/ 0x4 0x4 14971f34979SDavid Gibson /*RXDE*/ 0x5 0x4>; 1508bc4a51dSStefan Roese }; 1518bc4a51dSStefan Roese 1528bc4a51dSStefan Roese POB0: opb { 1538bc4a51dSStefan Roese compatible = "ibm,opb-460ex", "ibm,opb"; 1548bc4a51dSStefan Roese #address-cells = <1>; 1558bc4a51dSStefan Roese #size-cells = <1>; 15671f34979SDavid Gibson ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; 1578bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1588bc4a51dSStefan Roese 1598bc4a51dSStefan Roese EBC0: ebc { 1608bc4a51dSStefan Roese compatible = "ibm,ebc-460ex", "ibm,ebc"; 16171f34979SDavid Gibson dcr-reg = <0x012 0x002>; 1628bc4a51dSStefan Roese #address-cells = <2>; 1638bc4a51dSStefan Roese #size-cells = <1>; 1648bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 1655020231bSStefan Roese /* ranges property is supplied by U-Boot */ 16671f34979SDavid Gibson interrupts = <0x6 0x4>; 1678bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 1685020231bSStefan Roese 1695020231bSStefan Roese nor_flash@0,0 { 1705020231bSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 1715020231bSStefan Roese bank-width = <2>; 17271f34979SDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 1735020231bSStefan Roese #address-cells = <1>; 1745020231bSStefan Roese #size-cells = <1>; 1755020231bSStefan Roese partition@0 { 1765020231bSStefan Roese label = "kernel"; 17771f34979SDavid Gibson reg = <0x00000000 0x001e0000>; 1785020231bSStefan Roese }; 1795020231bSStefan Roese partition@1e0000 { 1805020231bSStefan Roese label = "dtb"; 18171f34979SDavid Gibson reg = <0x001e0000 0x00020000>; 1825020231bSStefan Roese }; 1835020231bSStefan Roese partition@200000 { 1845020231bSStefan Roese label = "ramdisk"; 18571f34979SDavid Gibson reg = <0x00200000 0x01400000>; 1865020231bSStefan Roese }; 1875020231bSStefan Roese partition@1600000 { 1885020231bSStefan Roese label = "jffs2"; 18971f34979SDavid Gibson reg = <0x01600000 0x00400000>; 1905020231bSStefan Roese }; 1915020231bSStefan Roese partition@1a00000 { 1925020231bSStefan Roese label = "user"; 19371f34979SDavid Gibson reg = <0x01a00000 0x02560000>; 1945020231bSStefan Roese }; 1955020231bSStefan Roese partition@3f60000 { 1965020231bSStefan Roese label = "env"; 19771f34979SDavid Gibson reg = <0x03f60000 0x00040000>; 1985020231bSStefan Roese }; 1995020231bSStefan Roese partition@3fa0000 { 2005020231bSStefan Roese label = "u-boot"; 20171f34979SDavid Gibson reg = <0x03fa0000 0x00060000>; 2025020231bSStefan Roese }; 2035020231bSStefan Roese }; 2048bc4a51dSStefan Roese }; 2058bc4a51dSStefan Roese 2068bc4a51dSStefan Roese UART0: serial@ef600300 { 2078bc4a51dSStefan Roese device_type = "serial"; 2088bc4a51dSStefan Roese compatible = "ns16550"; 20971f34979SDavid Gibson reg = <0xef600300 0x00000008>; 21071f34979SDavid Gibson virtual-reg = <0xef600300>; 2118bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2128bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2138bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 21471f34979SDavid Gibson interrupts = <0x1 0x4>; 2158bc4a51dSStefan Roese }; 2168bc4a51dSStefan Roese 2178bc4a51dSStefan Roese UART1: serial@ef600400 { 2188bc4a51dSStefan Roese device_type = "serial"; 2198bc4a51dSStefan Roese compatible = "ns16550"; 22071f34979SDavid Gibson reg = <0xef600400 0x00000008>; 22171f34979SDavid Gibson virtual-reg = <0xef600400>; 2228bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2238bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2248bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 22571f34979SDavid Gibson interrupts = <0x1 0x4>; 2268bc4a51dSStefan Roese }; 2278bc4a51dSStefan Roese 2288bc4a51dSStefan Roese UART2: serial@ef600500 { 2298bc4a51dSStefan Roese device_type = "serial"; 2308bc4a51dSStefan Roese compatible = "ns16550"; 23171f34979SDavid Gibson reg = <0xef600500 0x00000008>; 23271f34979SDavid Gibson virtual-reg = <0xef600500>; 2338bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2348bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2358bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 23671f34979SDavid Gibson interrupts = <0x1d 0x4>; 2378bc4a51dSStefan Roese }; 2388bc4a51dSStefan Roese 2398bc4a51dSStefan Roese UART3: serial@ef600600 { 2408bc4a51dSStefan Roese device_type = "serial"; 2418bc4a51dSStefan Roese compatible = "ns16550"; 24271f34979SDavid Gibson reg = <0xef600600 0x00000008>; 24371f34979SDavid Gibson virtual-reg = <0xef600600>; 2448bc4a51dSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 2458bc4a51dSStefan Roese current-speed = <0>; /* Filled in by U-Boot */ 2468bc4a51dSStefan Roese interrupt-parent = <&UIC1>; 24771f34979SDavid Gibson interrupts = <0x1e 0x4>; 2488bc4a51dSStefan Roese }; 2498bc4a51dSStefan Roese 2508bc4a51dSStefan Roese IIC0: i2c@ef600700 { 2518bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 25271f34979SDavid Gibson reg = <0xef600700 0x00000014>; 2538bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 25471f34979SDavid Gibson interrupts = <0x2 0x4>; 2558bc4a51dSStefan Roese }; 2568bc4a51dSStefan Roese 2578bc4a51dSStefan Roese IIC1: i2c@ef600800 { 2588bc4a51dSStefan Roese compatible = "ibm,iic-460ex", "ibm,iic"; 25971f34979SDavid Gibson reg = <0xef600800 0x00000014>; 2608bc4a51dSStefan Roese interrupt-parent = <&UIC0>; 26171f34979SDavid Gibson interrupts = <0x3 0x4>; 2628bc4a51dSStefan Roese }; 2638bc4a51dSStefan Roese 2648bc4a51dSStefan Roese ZMII0: emac-zmii@ef600d00 { 2658bc4a51dSStefan Roese compatible = "ibm,zmii-460ex", "ibm,zmii"; 26671f34979SDavid Gibson reg = <0xef600d00 0x0000000c>; 2678bc4a51dSStefan Roese }; 2688bc4a51dSStefan Roese 2698bc4a51dSStefan Roese RGMII0: emac-rgmii@ef601500 { 2708bc4a51dSStefan Roese compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 27171f34979SDavid Gibson reg = <0xef601500 0x00000008>; 2728bc4a51dSStefan Roese has-mdio; 2738bc4a51dSStefan Roese }; 2748bc4a51dSStefan Roese 275a6190a84SStefan Roese TAH0: emac-tah@ef601350 { 276a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 27771f34979SDavid Gibson reg = <0xef601350 0x00000030>; 278a6190a84SStefan Roese }; 279a6190a84SStefan Roese 280a6190a84SStefan Roese TAH1: emac-tah@ef601450 { 281a6190a84SStefan Roese compatible = "ibm,tah-460ex", "ibm,tah"; 28271f34979SDavid Gibson reg = <0xef601450 0x00000030>; 283a6190a84SStefan Roese }; 284a6190a84SStefan Roese 2858bc4a51dSStefan Roese EMAC0: ethernet@ef600e00 { 2868bc4a51dSStefan Roese device_type = "network"; 28705781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 2888bc4a51dSStefan Roese interrupt-parent = <&EMAC0>; 28971f34979SDavid Gibson interrupts = <0x0 0x1>; 2908bc4a51dSStefan Roese #interrupt-cells = <1>; 2918bc4a51dSStefan Roese #address-cells = <0>; 2928bc4a51dSStefan Roese #size-cells = <0>; 29371f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 29471f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x14 0x4>; 29505781ccdSGrant Erickson reg = <0xef600e00 0x000000c4>; 2968bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 2978bc4a51dSStefan Roese mal-device = <&MAL0>; 2988bc4a51dSStefan Roese mal-tx-channel = <0>; 2998bc4a51dSStefan Roese mal-rx-channel = <0>; 3008bc4a51dSStefan Roese cell-index = <0>; 30171f34979SDavid Gibson max-frame-size = <9000>; 30271f34979SDavid Gibson rx-fifo-size = <4096>; 30371f34979SDavid Gibson tx-fifo-size = <2048>; 3048bc4a51dSStefan Roese phy-mode = "rgmii"; 30571f34979SDavid Gibson phy-map = <0x00000000>; 3068bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3078bc4a51dSStefan Roese rgmii-channel = <0>; 308a6190a84SStefan Roese tah-device = <&TAH0>; 309a6190a84SStefan Roese tah-channel = <0>; 3108bc4a51dSStefan Roese has-inverted-stacr-oc; 3118bc4a51dSStefan Roese has-new-stacr-staopc; 3128bc4a51dSStefan Roese }; 3138bc4a51dSStefan Roese 3148bc4a51dSStefan Roese EMAC1: ethernet@ef600f00 { 3158bc4a51dSStefan Roese device_type = "network"; 31605781ccdSGrant Erickson compatible = "ibm,emac-460ex", "ibm,emac4sync"; 3178bc4a51dSStefan Roese interrupt-parent = <&EMAC1>; 31871f34979SDavid Gibson interrupts = <0x0 0x1>; 3198bc4a51dSStefan Roese #interrupt-cells = <1>; 3208bc4a51dSStefan Roese #address-cells = <0>; 3218bc4a51dSStefan Roese #size-cells = <0>; 32271f34979SDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 32371f34979SDavid Gibson /*Wake*/ 0x1 &UIC2 0x15 0x4>; 32405781ccdSGrant Erickson reg = <0xef600f00 0x000000c4>; 3258bc4a51dSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 3268bc4a51dSStefan Roese mal-device = <&MAL0>; 3278bc4a51dSStefan Roese mal-tx-channel = <1>; 3288bc4a51dSStefan Roese mal-rx-channel = <8>; 3298bc4a51dSStefan Roese cell-index = <1>; 33071f34979SDavid Gibson max-frame-size = <9000>; 33171f34979SDavid Gibson rx-fifo-size = <4096>; 33271f34979SDavid Gibson tx-fifo-size = <2048>; 3338bc4a51dSStefan Roese phy-mode = "rgmii"; 33471f34979SDavid Gibson phy-map = <0x00000000>; 3358bc4a51dSStefan Roese rgmii-device = <&RGMII0>; 3368bc4a51dSStefan Roese rgmii-channel = <1>; 337a6190a84SStefan Roese tah-device = <&TAH1>; 338a6190a84SStefan Roese tah-channel = <1>; 3398bc4a51dSStefan Roese has-inverted-stacr-oc; 3408bc4a51dSStefan Roese has-new-stacr-staopc; 341a6190a84SStefan Roese mdio-device = <&EMAC0>; 3428bc4a51dSStefan Roese }; 3438bc4a51dSStefan Roese }; 3448bc4a51dSStefan Roese 3458bc4a51dSStefan Roese PCIX0: pci@c0ec00000 { 3468bc4a51dSStefan Roese device_type = "pci"; 3478bc4a51dSStefan Roese #interrupt-cells = <1>; 3488bc4a51dSStefan Roese #size-cells = <2>; 3498bc4a51dSStefan Roese #address-cells = <3>; 3508bc4a51dSStefan Roese compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; 3518bc4a51dSStefan Roese primary; 3528bc4a51dSStefan Roese large-inbound-windows; 3538bc4a51dSStefan Roese enable-msi-hole; 35471f34979SDavid Gibson reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ 35571f34979SDavid Gibson 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 35671f34979SDavid Gibson 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ 35771f34979SDavid Gibson 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ 35871f34979SDavid Gibson 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 3598bc4a51dSStefan Roese 3608bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3618bc4a51dSStefan Roese * later cannot be changed 3628bc4a51dSStefan Roese */ 36371f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 36484d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 36571f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; 3668bc4a51dSStefan Roese 3678bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 36871f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 3698bc4a51dSStefan Roese 3708bc4a51dSStefan Roese /* This drives busses 0 to 0x3f */ 37171f34979SDavid Gibson bus-range = <0x0 0x3f>; 3728bc4a51dSStefan Roese 3738bc4a51dSStefan Roese /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 37471f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x0>; 37571f34979SDavid Gibson interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; 3768bc4a51dSStefan Roese }; 3778bc4a51dSStefan Roese 3788bc4a51dSStefan Roese PCIE0: pciex@d00000000 { 3798bc4a51dSStefan Roese device_type = "pci"; 3808bc4a51dSStefan Roese #interrupt-cells = <1>; 3818bc4a51dSStefan Roese #size-cells = <2>; 3828bc4a51dSStefan Roese #address-cells = <3>; 3838bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 3848bc4a51dSStefan Roese primary; 38571f34979SDavid Gibson port = <0x0>; /* port number */ 38671f34979SDavid Gibson reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 38771f34979SDavid Gibson 0x0000000c 0x08010000 0x00001000>; /* Registers */ 38871f34979SDavid Gibson dcr-reg = <0x100 0x020>; 38971f34979SDavid Gibson sdr-base = <0x300>; 3908bc4a51dSStefan Roese 3918bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 3928bc4a51dSStefan Roese * later cannot be changed 3938bc4a51dSStefan Roese */ 39471f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 39584d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 39671f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; 3978bc4a51dSStefan Roese 3988bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 39971f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4008bc4a51dSStefan Roese 4018bc4a51dSStefan Roese /* This drives busses 40 to 0x7f */ 40271f34979SDavid Gibson bus-range = <0x40 0x7f>; 4038bc4a51dSStefan Roese 4048bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4058bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4068bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4078bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4088bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4098bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4108bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4118bc4a51dSStefan Roese */ 41271f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4138bc4a51dSStefan Roese interrupt-map = < 41471f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 41571f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 41671f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 41771f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; 4188bc4a51dSStefan Roese }; 4198bc4a51dSStefan Roese 4208bc4a51dSStefan Roese PCIE1: pciex@d20000000 { 4218bc4a51dSStefan Roese device_type = "pci"; 4228bc4a51dSStefan Roese #interrupt-cells = <1>; 4238bc4a51dSStefan Roese #size-cells = <2>; 4248bc4a51dSStefan Roese #address-cells = <3>; 4258bc4a51dSStefan Roese compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 4268bc4a51dSStefan Roese primary; 42771f34979SDavid Gibson port = <0x1>; /* port number */ 42871f34979SDavid Gibson reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ 42971f34979SDavid Gibson 0x0000000c 0x08011000 0x00001000>; /* Registers */ 43071f34979SDavid Gibson dcr-reg = <0x120 0x020>; 43171f34979SDavid Gibson sdr-base = <0x340>; 4328bc4a51dSStefan Roese 4338bc4a51dSStefan Roese /* Outbound ranges, one memory and one IO, 4348bc4a51dSStefan Roese * later cannot be changed 4358bc4a51dSStefan Roese */ 43671f34979SDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 43784d727a1SBenjamin Herrenschmidt 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 43871f34979SDavid Gibson 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; 4398bc4a51dSStefan Roese 4408bc4a51dSStefan Roese /* Inbound 2GB range starting at 0 */ 44171f34979SDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 4428bc4a51dSStefan Roese 4438bc4a51dSStefan Roese /* This drives busses 80 to 0xbf */ 44471f34979SDavid Gibson bus-range = <0x80 0xbf>; 4458bc4a51dSStefan Roese 4468bc4a51dSStefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 4478bc4a51dSStefan Roese * to invert PCIe legacy interrupts). 4488bc4a51dSStefan Roese * We are de-swizzling here because the numbers are actually for 4498bc4a51dSStefan Roese * port of the root complex virtual P2P bridge. But I want 4508bc4a51dSStefan Roese * to avoid putting a node for it in the tree, so the numbers 4518bc4a51dSStefan Roese * below are basically de-swizzled numbers. 4528bc4a51dSStefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 4538bc4a51dSStefan Roese */ 45471f34979SDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 4558bc4a51dSStefan Roese interrupt-map = < 45671f34979SDavid Gibson 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ 45771f34979SDavid Gibson 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ 45871f34979SDavid Gibson 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ 45971f34979SDavid Gibson 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; 4608bc4a51dSStefan Roese }; 4618bc4a51dSStefan Roese }; 4628bc4a51dSStefan Roese}; 463