1 /* $Id: pci.c,v 1.6 2000/01/29 00:12:05 grundler Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1997, 1998 Ralf Baechle 8 * Copyright (C) 1999 SuSE GmbH 9 * Copyright (C) 1999-2001 Hewlett-Packard Company 10 * Copyright (C) 1999-2001 Grant Grundler 11 */ 12 #include <linux/config.h> 13 #include <linux/eisa.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #include <asm/io.h> 22 #include <asm/system.h> 23 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 24 #include <asm/superio.h> 25 26 #define DEBUG_RESOURCES 0 27 #define DEBUG_CONFIG 0 28 29 #if DEBUG_CONFIG 30 # define DBGC(x...) printk(KERN_DEBUG x) 31 #else 32 # define DBGC(x...) 33 #endif 34 35 36 #if DEBUG_RESOURCES 37 #define DBG_RES(x...) printk(KERN_DEBUG x) 38 #else 39 #define DBG_RES(x...) 40 #endif 41 42 /* To be used as: mdelay(pci_post_reset_delay); 43 * 44 * post_reset is the time the kernel should stall to prevent anyone from 45 * accessing the PCI bus once #RESET is de-asserted. 46 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 47 * this makes the boot time much longer than necessary. 48 * 20ms seems to work for all the HP PCI implementations to date. 49 * 50 * #define pci_post_reset_delay 50 51 */ 52 53 struct pci_port_ops *pci_port __read_mostly; 54 struct pci_bios_ops *pci_bios __read_mostly; 55 56 static int pci_hba_count __read_mostly; 57 58 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ 59 #define PCI_HBA_MAX 32 60 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly; 61 62 63 /******************************************************************** 64 ** 65 ** I/O port space support 66 ** 67 *********************************************************************/ 68 69 /* EISA port numbers and PCI port numbers share the same interface. Some 70 * machines have both EISA and PCI adapters installed. Rather than turn 71 * pci_port into an array, we reserve bus 0 for EISA and call the EISA 72 * routines if the access is to a port on bus 0. We don't want to fix 73 * EISA and ISA drivers which assume port space is <= 0xffff. 74 */ 75 76 #ifdef CONFIG_EISA 77 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) 78 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) 79 #else 80 #define EISA_IN(size) 81 #define EISA_OUT(size) 82 #endif 83 84 #define PCI_PORT_IN(type, size) \ 85 u##size in##type (int addr) \ 86 { \ 87 int b = PCI_PORT_HBA(addr); \ 88 EISA_IN(size); \ 89 if (!parisc_pci_hba[b]) return (u##size) -1; \ 90 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ 91 } \ 92 EXPORT_SYMBOL(in##type); 93 94 PCI_PORT_IN(b, 8) 95 PCI_PORT_IN(w, 16) 96 PCI_PORT_IN(l, 32) 97 98 99 #define PCI_PORT_OUT(type, size) \ 100 void out##type (u##size d, int addr) \ 101 { \ 102 int b = PCI_PORT_HBA(addr); \ 103 EISA_OUT(size); \ 104 if (!parisc_pci_hba[b]) return; \ 105 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ 106 } \ 107 EXPORT_SYMBOL(out##type); 108 109 PCI_PORT_OUT(b, 8) 110 PCI_PORT_OUT(w, 16) 111 PCI_PORT_OUT(l, 32) 112 113 114 115 /* 116 * BIOS32 replacement. 117 */ 118 static int __init pcibios_init(void) 119 { 120 if (!pci_bios) 121 return -1; 122 123 if (pci_bios->init) { 124 pci_bios->init(); 125 } else { 126 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 127 } 128 return 0; 129 } 130 131 132 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ 133 void pcibios_fixup_bus(struct pci_bus *bus) 134 { 135 if (pci_bios->fixup_bus) { 136 pci_bios->fixup_bus(bus); 137 } else { 138 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n"); 139 } 140 } 141 142 143 char *pcibios_setup(char *str) 144 { 145 return str; 146 } 147 148 /* 149 * Called by pci_set_master() - a driver interface. 150 * 151 * Legacy PDC guarantees to set: 152 * Map Memory BAR's into PA IO space. 153 * Map Expansion ROM BAR into one common PA IO space per bus. 154 * Map IO BAR's into PCI IO space. 155 * Command (see below) 156 * Cache Line Size 157 * Latency Timer 158 * Interrupt Line 159 * PPB: secondary latency timer, io/mmio base/limit, 160 * bus numbers, bridge control 161 * 162 */ 163 void pcibios_set_master(struct pci_dev *dev) 164 { 165 u8 lat; 166 167 /* If someone already mucked with this, don't touch it. */ 168 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 169 if (lat >= 16) return; 170 171 /* 172 ** HP generally has fewer devices on the bus than other architectures. 173 ** upper byte is PCI_LATENCY_TIMER. 174 */ 175 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 176 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); 177 } 178 179 180 void __init pcibios_init_bus(struct pci_bus *bus) 181 { 182 struct pci_dev *dev = bus->self; 183 unsigned short bridge_ctl; 184 185 /* We deal only with pci controllers and pci-pci bridges. */ 186 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 187 return; 188 189 /* PCI-PCI bridge - set the cache line and default latency 190 (32) for primary and secondary buses. */ 191 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); 192 193 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); 194 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 195 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); 196 } 197 198 199 /* KLUGE: Link the child and parent resources - generic PCI didn't */ 200 static void 201 pcibios_link_hba_resources( struct resource *hba_res, struct resource *r) 202 { 203 if (!r->parent) { 204 printk(KERN_EMERG "PCI: resource not parented! [%lx-%lx]\n", 205 r->start, r->end); 206 r->parent = hba_res; 207 208 /* reverse link is harder *sigh* */ 209 if (r->parent->child) { 210 if (r->parent->sibling) { 211 struct resource *next = r->parent->sibling; 212 while (next->sibling) 213 next = next->sibling; 214 next->sibling = r; 215 } else { 216 r->parent->sibling = r; 217 } 218 } else 219 r->parent->child = r; 220 } 221 } 222 223 /* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */ 224 void __devinit pcibios_resource_to_bus(struct pci_dev *dev, 225 struct pci_bus_region *region, struct resource *res) 226 { 227 struct pci_bus *bus = dev->bus; 228 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 229 230 if (res->flags & IORESOURCE_IO) { 231 /* 232 ** I/O space may see busnumbers here. Something 233 ** in the form of 0xbbxxxx where bb is the bus num 234 ** and xxxx is the I/O port space address. 235 ** Remaining address translation are done in the 236 ** PCI Host adapter specific code - ie dino_out8. 237 */ 238 region->start = PCI_PORT_ADDR(res->start); 239 region->end = PCI_PORT_ADDR(res->end); 240 } else if (res->flags & IORESOURCE_MEM) { 241 /* Convert MMIO addr to PCI addr (undo global virtualization) */ 242 region->start = PCI_BUS_ADDR(hba, res->start); 243 region->end = PCI_BUS_ADDR(hba, res->end); 244 } 245 246 DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n", 247 bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM", 248 region->start, region->end); 249 250 /* KLUGE ALERT 251 ** if this resource isn't linked to a "parent", then it seems 252 ** to be a child of the HBA - lets link it in. 253 */ 254 pcibios_link_hba_resources(&hba->io_space, bus->resource[0]); 255 pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]); 256 } 257 258 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 259 struct pci_bus_region *region) 260 { 261 #ifdef CONFIG_64BIT 262 struct pci_bus *bus = dev->bus; 263 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 264 #endif 265 266 if (res->flags & IORESOURCE_MEM) { 267 res->start = PCI_HOST_ADDR(hba, region->start); 268 res->end = PCI_HOST_ADDR(hba, region->end); 269 } 270 271 if (res->flags & IORESOURCE_IO) { 272 res->start = region->start; 273 res->end = region->end; 274 } 275 } 276 277 #ifdef CONFIG_HOTPLUG 278 EXPORT_SYMBOL(pcibios_resource_to_bus); 279 EXPORT_SYMBOL(pcibios_bus_to_resource); 280 #endif 281 282 /* 283 * pcibios align resources() is called every time generic PCI code 284 * wants to generate a new address. The process of looking for 285 * an available address, each candidate is first "aligned" and 286 * then checked if the resource is available until a match is found. 287 * 288 * Since we are just checking candidates, don't use any fields other 289 * than res->start. 290 */ 291 void pcibios_align_resource(void *data, struct resource *res, 292 unsigned long size, unsigned long alignment) 293 { 294 unsigned long mask, align; 295 296 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n", 297 pci_name(((struct pci_dev *) data)), 298 res->parent, res->start, res->end, 299 (int) res->flags, size, alignment); 300 301 /* If it's not IO, then it's gotta be MEM */ 302 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 303 304 /* Align to largest of MIN or input size */ 305 mask = max(alignment, align) - 1; 306 res->start += mask; 307 res->start &= ~mask; 308 309 /* The caller updates the end field, we don't. */ 310 } 311 312 313 /* 314 * A driver is enabling the device. We make sure that all the appropriate 315 * bits are set to allow the device to operate as the driver is expecting. 316 * We enable the port IO and memory IO bits if the device has any BARs of 317 * that type, and we enable the PERR and SERR bits unconditionally. 318 * Drivers that do not need parity (eg graphics and possibly networking) 319 * can clear these bits if they want. 320 */ 321 int pcibios_enable_device(struct pci_dev *dev, int mask) 322 { 323 u16 cmd; 324 int idx; 325 326 pci_read_config_word(dev, PCI_COMMAND, &cmd); 327 328 for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) { 329 struct resource *r = &dev->resource[idx]; 330 331 /* only setup requested resources */ 332 if (!(mask & (1<<idx))) 333 continue; 334 335 if (r->flags & IORESOURCE_IO) 336 cmd |= PCI_COMMAND_IO; 337 if (r->flags & IORESOURCE_MEM) 338 cmd |= PCI_COMMAND_MEMORY; 339 } 340 341 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 342 343 #if 0 344 /* If bridge/bus controller has FBB enabled, child must too. */ 345 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK) 346 cmd |= PCI_COMMAND_FAST_BACK; 347 #endif 348 DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd); 349 pci_write_config_word(dev, PCI_COMMAND, cmd); 350 return 0; 351 } 352 353 354 /* PA-RISC specific */ 355 void pcibios_register_hba(struct pci_hba_data *hba) 356 { 357 if (pci_hba_count >= PCI_HBA_MAX) { 358 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n"); 359 return; 360 } 361 362 parisc_pci_hba[pci_hba_count] = hba; 363 hba->hba_num = pci_hba_count++; 364 } 365 366 subsys_initcall(pcibios_init); 367