1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1997, 1998 Ralf Baechle 7 * Copyright (C) 1999 SuSE GmbH 8 * Copyright (C) 1999-2001 Hewlett-Packard Company 9 * Copyright (C) 1999-2001 Grant Grundler 10 */ 11 #include <linux/eisa.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/types.h> 17 18 #include <asm/io.h> 19 #include <asm/superio.h> 20 21 #define DEBUG_RESOURCES 0 22 #define DEBUG_CONFIG 0 23 24 #if DEBUG_CONFIG 25 # define DBGC(x...) printk(KERN_DEBUG x) 26 #else 27 # define DBGC(x...) 28 #endif 29 30 31 #if DEBUG_RESOURCES 32 #define DBG_RES(x...) printk(KERN_DEBUG x) 33 #else 34 #define DBG_RES(x...) 35 #endif 36 37 /* To be used as: mdelay(pci_post_reset_delay); 38 * 39 * post_reset is the time the kernel should stall to prevent anyone from 40 * accessing the PCI bus once #RESET is de-asserted. 41 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 42 * this makes the boot time much longer than necessary. 43 * 20ms seems to work for all the HP PCI implementations to date. 44 * 45 * #define pci_post_reset_delay 50 46 */ 47 48 struct pci_port_ops *pci_port __read_mostly; 49 struct pci_bios_ops *pci_bios __read_mostly; 50 51 static int pci_hba_count __read_mostly; 52 53 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ 54 #define PCI_HBA_MAX 32 55 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly; 56 57 58 /******************************************************************** 59 ** 60 ** I/O port space support 61 ** 62 *********************************************************************/ 63 64 /* EISA port numbers and PCI port numbers share the same interface. Some 65 * machines have both EISA and PCI adapters installed. Rather than turn 66 * pci_port into an array, we reserve bus 0 for EISA and call the EISA 67 * routines if the access is to a port on bus 0. We don't want to fix 68 * EISA and ISA drivers which assume port space is <= 0xffff. 69 */ 70 71 #ifdef CONFIG_EISA 72 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) 73 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) 74 #else 75 #define EISA_IN(size) 76 #define EISA_OUT(size) 77 #endif 78 79 #define PCI_PORT_IN(type, size) \ 80 u##size in##type (int addr) \ 81 { \ 82 int b = PCI_PORT_HBA(addr); \ 83 EISA_IN(size); \ 84 if (!parisc_pci_hba[b]) return (u##size) -1; \ 85 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ 86 } \ 87 EXPORT_SYMBOL(in##type); 88 89 PCI_PORT_IN(b, 8) 90 PCI_PORT_IN(w, 16) 91 PCI_PORT_IN(l, 32) 92 93 94 #define PCI_PORT_OUT(type, size) \ 95 void out##type (u##size d, int addr) \ 96 { \ 97 int b = PCI_PORT_HBA(addr); \ 98 EISA_OUT(size); \ 99 if (!parisc_pci_hba[b]) return; \ 100 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ 101 } \ 102 EXPORT_SYMBOL(out##type); 103 104 PCI_PORT_OUT(b, 8) 105 PCI_PORT_OUT(w, 16) 106 PCI_PORT_OUT(l, 32) 107 108 109 110 /* 111 * BIOS32 replacement. 112 */ 113 static int __init pcibios_init(void) 114 { 115 if (!pci_bios) 116 return -1; 117 118 if (pci_bios->init) { 119 pci_bios->init(); 120 } else { 121 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 122 } 123 124 /* Set the CLS for PCI as early as possible. */ 125 pci_cache_line_size = pci_dfl_cache_line_size; 126 127 return 0; 128 } 129 130 131 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ 132 void pcibios_fixup_bus(struct pci_bus *bus) 133 { 134 if (pci_bios->fixup_bus) { 135 pci_bios->fixup_bus(bus); 136 } else { 137 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n"); 138 } 139 } 140 141 142 char *pcibios_setup(char *str) 143 { 144 return str; 145 } 146 147 /* 148 * Called by pci_set_master() - a driver interface. 149 * 150 * Legacy PDC guarantees to set: 151 * Map Memory BAR's into PA IO space. 152 * Map Expansion ROM BAR into one common PA IO space per bus. 153 * Map IO BAR's into PCI IO space. 154 * Command (see below) 155 * Cache Line Size 156 * Latency Timer 157 * Interrupt Line 158 * PPB: secondary latency timer, io/mmio base/limit, 159 * bus numbers, bridge control 160 * 161 */ 162 void pcibios_set_master(struct pci_dev *dev) 163 { 164 u8 lat; 165 166 /* If someone already mucked with this, don't touch it. */ 167 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 168 if (lat >= 16) return; 169 170 /* 171 ** HP generally has fewer devices on the bus than other architectures. 172 ** upper byte is PCI_LATENCY_TIMER. 173 */ 174 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 175 (0x80 << 8) | pci_cache_line_size); 176 } 177 178 179 void __init pcibios_init_bus(struct pci_bus *bus) 180 { 181 struct pci_dev *dev = bus->self; 182 unsigned short bridge_ctl; 183 184 /* We deal only with pci controllers and pci-pci bridges. */ 185 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 186 return; 187 188 /* PCI-PCI bridge - set the cache line and default latency 189 (32) for primary and secondary buses. */ 190 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); 191 192 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); 193 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 194 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); 195 } 196 197 /* 198 * pcibios align resources() is called every time generic PCI code 199 * wants to generate a new address. The process of looking for 200 * an available address, each candidate is first "aligned" and 201 * then checked if the resource is available until a match is found. 202 * 203 * Since we are just checking candidates, don't use any fields other 204 * than res->start. 205 */ 206 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 207 resource_size_t size, resource_size_t alignment) 208 { 209 resource_size_t mask, align, start = res->start; 210 211 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n", 212 pci_name(((struct pci_dev *) data)), 213 res->parent, res->start, res->end, 214 (int) res->flags, size, alignment); 215 216 /* If it's not IO, then it's gotta be MEM */ 217 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 218 219 /* Align to largest of MIN or input size */ 220 mask = max(alignment, align) - 1; 221 start += mask; 222 start &= ~mask; 223 224 return start; 225 } 226 227 228 /* 229 * A driver is enabling the device. We make sure that all the appropriate 230 * bits are set to allow the device to operate as the driver is expecting. 231 * We enable the port IO and memory IO bits if the device has any BARs of 232 * that type, and we enable the PERR and SERR bits unconditionally. 233 * Drivers that do not need parity (eg graphics and possibly networking) 234 * can clear these bits if they want. 235 */ 236 int pcibios_enable_device(struct pci_dev *dev, int mask) 237 { 238 int err; 239 u16 cmd, old_cmd; 240 241 err = pci_enable_resources(dev, mask); 242 if (err < 0) 243 return err; 244 245 pci_read_config_word(dev, PCI_COMMAND, &cmd); 246 old_cmd = cmd; 247 248 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 249 250 #if 0 251 /* If bridge/bus controller has FBB enabled, child must too. */ 252 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK) 253 cmd |= PCI_COMMAND_FAST_BACK; 254 #endif 255 256 if (cmd != old_cmd) { 257 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n", 258 old_cmd, cmd); 259 pci_write_config_word(dev, PCI_COMMAND, cmd); 260 } 261 return 0; 262 } 263 264 265 /* PA-RISC specific */ 266 void pcibios_register_hba(struct pci_hba_data *hba) 267 { 268 if (pci_hba_count >= PCI_HBA_MAX) { 269 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n"); 270 return; 271 } 272 273 parisc_pci_hba[pci_hba_count] = hba; 274 hba->hba_num = pci_hba_count++; 275 } 276 277 subsys_initcall(pcibios_init); 278