1 /* $Id: pci.c,v 1.6 2000/01/29 00:12:05 grundler Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1997, 1998 Ralf Baechle 8 * Copyright (C) 1999 SuSE GmbH 9 * Copyright (C) 1999-2001 Hewlett-Packard Company 10 * Copyright (C) 1999-2001 Grant Grundler 11 */ 12 #include <linux/config.h> 13 #include <linux/eisa.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #include <asm/io.h> 22 #include <asm/system.h> 23 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 24 #include <asm/superio.h> 25 26 #define DEBUG_RESOURCES 0 27 #define DEBUG_CONFIG 0 28 29 #if DEBUG_CONFIG 30 # define DBGC(x...) printk(KERN_DEBUG x) 31 #else 32 # define DBGC(x...) 33 #endif 34 35 36 #if DEBUG_RESOURCES 37 #define DBG_RES(x...) printk(KERN_DEBUG x) 38 #else 39 #define DBG_RES(x...) 40 #endif 41 42 /* To be used as: mdelay(pci_post_reset_delay); 43 * 44 * post_reset is the time the kernel should stall to prevent anyone from 45 * accessing the PCI bus once #RESET is de-asserted. 46 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 47 * this makes the boot time much longer than necessary. 48 * 20ms seems to work for all the HP PCI implementations to date. 49 * 50 * XXX: turn into a #defined constant in <asm/pci.h> ? 51 */ 52 int pci_post_reset_delay = 50; 53 54 struct pci_port_ops *pci_port; 55 struct pci_bios_ops *pci_bios; 56 57 int pci_hba_count = 0; 58 59 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ 60 #define PCI_HBA_MAX 32 61 struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX]; 62 63 64 /******************************************************************** 65 ** 66 ** I/O port space support 67 ** 68 *********************************************************************/ 69 70 /* EISA port numbers and PCI port numbers share the same interface. Some 71 * machines have both EISA and PCI adapters installed. Rather than turn 72 * pci_port into an array, we reserve bus 0 for EISA and call the EISA 73 * routines if the access is to a port on bus 0. We don't want to fix 74 * EISA and ISA drivers which assume port space is <= 0xffff. 75 */ 76 77 #ifdef CONFIG_EISA 78 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) 79 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) 80 #else 81 #define EISA_IN(size) 82 #define EISA_OUT(size) 83 #endif 84 85 #define PCI_PORT_IN(type, size) \ 86 u##size in##type (int addr) \ 87 { \ 88 int b = PCI_PORT_HBA(addr); \ 89 EISA_IN(size); \ 90 if (!parisc_pci_hba[b]) return (u##size) -1; \ 91 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ 92 } \ 93 EXPORT_SYMBOL(in##type); 94 95 PCI_PORT_IN(b, 8) 96 PCI_PORT_IN(w, 16) 97 PCI_PORT_IN(l, 32) 98 99 100 #define PCI_PORT_OUT(type, size) \ 101 void out##type (u##size d, int addr) \ 102 { \ 103 int b = PCI_PORT_HBA(addr); \ 104 EISA_OUT(size); \ 105 if (!parisc_pci_hba[b]) return; \ 106 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ 107 } \ 108 EXPORT_SYMBOL(out##type); 109 110 PCI_PORT_OUT(b, 8) 111 PCI_PORT_OUT(w, 16) 112 PCI_PORT_OUT(l, 32) 113 114 115 116 /* 117 * BIOS32 replacement. 118 */ 119 static int __init pcibios_init(void) 120 { 121 if (!pci_bios) 122 return -1; 123 124 if (pci_bios->init) { 125 pci_bios->init(); 126 } else { 127 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 128 } 129 return 0; 130 } 131 132 133 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ 134 void pcibios_fixup_bus(struct pci_bus *bus) 135 { 136 if (pci_bios->fixup_bus) { 137 pci_bios->fixup_bus(bus); 138 } else { 139 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n"); 140 } 141 } 142 143 144 char *pcibios_setup(char *str) 145 { 146 return str; 147 } 148 149 /* 150 * Called by pci_set_master() - a driver interface. 151 * 152 * Legacy PDC guarantees to set: 153 * Map Memory BAR's into PA IO space. 154 * Map Expansion ROM BAR into one common PA IO space per bus. 155 * Map IO BAR's into PCI IO space. 156 * Command (see below) 157 * Cache Line Size 158 * Latency Timer 159 * Interrupt Line 160 * PPB: secondary latency timer, io/mmio base/limit, 161 * bus numbers, bridge control 162 * 163 */ 164 void pcibios_set_master(struct pci_dev *dev) 165 { 166 u8 lat; 167 168 /* If someone already mucked with this, don't touch it. */ 169 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 170 if (lat >= 16) return; 171 172 /* 173 ** HP generally has fewer devices on the bus than other architectures. 174 ** upper byte is PCI_LATENCY_TIMER. 175 */ 176 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 177 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); 178 } 179 180 181 void __init pcibios_init_bus(struct pci_bus *bus) 182 { 183 struct pci_dev *dev = bus->self; 184 unsigned short bridge_ctl; 185 186 /* We deal only with pci controllers and pci-pci bridges. */ 187 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 188 return; 189 190 /* PCI-PCI bridge - set the cache line and default latency 191 (32) for primary and secondary buses. */ 192 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); 193 194 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); 195 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 196 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); 197 } 198 199 200 /* KLUGE: Link the child and parent resources - generic PCI didn't */ 201 static void 202 pcibios_link_hba_resources( struct resource *hba_res, struct resource *r) 203 { 204 if (!r->parent) { 205 printk(KERN_EMERG "PCI: Tell willy he's wrong\n"); 206 r->parent = hba_res; 207 208 /* reverse link is harder *sigh* */ 209 if (r->parent->child) { 210 if (r->parent->sibling) { 211 struct resource *next = r->parent->sibling; 212 while (next->sibling) 213 next = next->sibling; 214 next->sibling = r; 215 } else { 216 r->parent->sibling = r; 217 } 218 } else 219 r->parent->child = r; 220 } 221 } 222 223 /* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */ 224 void __devinit pcibios_resource_to_bus(struct pci_dev *dev, 225 struct pci_bus_region *region, struct resource *res) 226 { 227 struct pci_bus *bus = dev->bus; 228 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 229 230 if (res->flags & IORESOURCE_IO) { 231 /* 232 ** I/O space may see busnumbers here. Something 233 ** in the form of 0xbbxxxx where bb is the bus num 234 ** and xxxx is the I/O port space address. 235 ** Remaining address translation are done in the 236 ** PCI Host adapter specific code - ie dino_out8. 237 */ 238 region->start = PCI_PORT_ADDR(res->start); 239 region->end = PCI_PORT_ADDR(res->end); 240 } else if (res->flags & IORESOURCE_MEM) { 241 /* Convert MMIO addr to PCI addr (undo global virtualization) */ 242 region->start = PCI_BUS_ADDR(hba, res->start); 243 region->end = PCI_BUS_ADDR(hba, res->end); 244 } 245 246 DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n", 247 bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM", 248 region->start, region->end); 249 250 /* KLUGE ALERT 251 ** if this resource isn't linked to a "parent", then it seems 252 ** to be a child of the HBA - lets link it in. 253 */ 254 pcibios_link_hba_resources(&hba->io_space, bus->resource[0]); 255 pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]); 256 } 257 258 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 259 struct pci_bus_region *region) 260 { 261 struct pci_bus *bus = dev->bus; 262 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 263 264 if (res->flags & IORESOURCE_MEM) { 265 res->start = PCI_HOST_ADDR(hba, region->start); 266 res->end = PCI_HOST_ADDR(hba, region->end); 267 } 268 269 if (res->flags & IORESOURCE_IO) { 270 res->start = region->start; 271 res->end = region->end; 272 } 273 } 274 275 #ifdef CONFIG_HOTPLUG 276 EXPORT_SYMBOL(pcibios_resource_to_bus); 277 EXPORT_SYMBOL(pcibios_bus_to_resource); 278 #endif 279 280 /* 281 * pcibios align resources() is called every time generic PCI code 282 * wants to generate a new address. The process of looking for 283 * an available address, each candidate is first "aligned" and 284 * then checked if the resource is available until a match is found. 285 * 286 * Since we are just checking candidates, don't use any fields other 287 * than res->start. 288 */ 289 void pcibios_align_resource(void *data, struct resource *res, 290 unsigned long size, unsigned long alignment) 291 { 292 unsigned long mask, align; 293 294 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n", 295 pci_name(((struct pci_dev *) data)), 296 res->parent, res->start, res->end, 297 (int) res->flags, size, alignment); 298 299 /* If it's not IO, then it's gotta be MEM */ 300 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 301 302 /* Align to largest of MIN or input size */ 303 mask = max(alignment, align) - 1; 304 res->start += mask; 305 res->start &= ~mask; 306 307 /* The caller updates the end field, we don't. */ 308 } 309 310 311 /* 312 * A driver is enabling the device. We make sure that all the appropriate 313 * bits are set to allow the device to operate as the driver is expecting. 314 * We enable the port IO and memory IO bits if the device has any BARs of 315 * that type, and we enable the PERR and SERR bits unconditionally. 316 * Drivers that do not need parity (eg graphics and possibly networking) 317 * can clear these bits if they want. 318 */ 319 int pcibios_enable_device(struct pci_dev *dev, int mask) 320 { 321 u16 cmd; 322 int idx; 323 324 pci_read_config_word(dev, PCI_COMMAND, &cmd); 325 326 for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) { 327 struct resource *r = &dev->resource[idx]; 328 329 /* only setup requested resources */ 330 if (!(mask & (1<<idx))) 331 continue; 332 333 if (r->flags & IORESOURCE_IO) 334 cmd |= PCI_COMMAND_IO; 335 if (r->flags & IORESOURCE_MEM) 336 cmd |= PCI_COMMAND_MEMORY; 337 } 338 339 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 340 341 #if 0 342 /* If bridge/bus controller has FBB enabled, child must too. */ 343 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK) 344 cmd |= PCI_COMMAND_FAST_BACK; 345 #endif 346 DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd); 347 pci_write_config_word(dev, PCI_COMMAND, cmd); 348 return 0; 349 } 350 351 352 /* PA-RISC specific */ 353 void pcibios_register_hba(struct pci_hba_data *hba) 354 { 355 if (pci_hba_count >= PCI_HBA_MAX) { 356 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n"); 357 return; 358 } 359 360 parisc_pci_hba[pci_hba_count] = hba; 361 hba->hba_num = pci_hba_count++; 362 } 363 364 subsys_initcall(pcibios_init); 365