1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _PARISC_PGTABLE_H 3 #define _PARISC_PGTABLE_H 4 5 #include <asm/page.h> 6 7 #if CONFIG_PGTABLE_LEVELS == 3 8 #include <asm-generic/pgtable-nopud.h> 9 #elif CONFIG_PGTABLE_LEVELS == 2 10 #include <asm-generic/pgtable-nopmd.h> 11 #endif 12 13 #include <asm/fixmap.h> 14 15 #ifndef __ASSEMBLER__ 16 /* 17 * we simulate an x86-style page table for the linux mm code 18 */ 19 20 #include <linux/bitops.h> 21 #include <linux/spinlock.h> 22 #include <linux/mm_types.h> 23 #include <asm/processor.h> 24 #include <asm/cache.h> 25 26 /* This is for the serialization of PxTLB broadcasts. At least on the N class 27 * systems, only one PxTLB inter processor broadcast can be active at any one 28 * time on the Merced bus. */ 29 extern spinlock_t pa_tlb_flush_lock; 30 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP) 31 extern int pa_serialize_tlb_flushes; 32 #else 33 #define pa_serialize_tlb_flushes (0) 34 #endif 35 36 #define purge_tlb_start(flags) do { \ 37 if (pa_serialize_tlb_flushes) \ 38 spin_lock_irqsave(&pa_tlb_flush_lock, flags); \ 39 else \ 40 local_irq_save(flags); \ 41 } while (0) 42 #define purge_tlb_end(flags) do { \ 43 if (pa_serialize_tlb_flushes) \ 44 spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \ 45 else \ 46 local_irq_restore(flags); \ 47 } while (0) 48 49 /* Purge data and instruction TLB entries. The TLB purge instructions 50 * are slow on SMP machines since the purge must be broadcast to all CPUs. 51 */ 52 53 static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr) 54 { 55 unsigned long flags; 56 57 purge_tlb_start(flags); 58 mtsp(mm->context.space_id, SR_TEMP1); 59 pdtlb(SR_TEMP1, addr); 60 pitlb(SR_TEMP1, addr); 61 purge_tlb_end(flags); 62 } 63 64 extern void __update_cache(pte_t pte); 65 66 /* Certain architectures need to do special things when PTEs 67 * within a page table are directly modified. Thus, the following 68 * hook is made available. 69 */ 70 #define set_pte(pteptr, pteval) \ 71 do { \ 72 *(pteptr) = (pteval); \ 73 mb(); \ 74 } while(0) 75 76 #endif /* !__ASSEMBLER__ */ 77 78 /* This is the size of the initially mapped kernel memory */ 79 #if defined(CONFIG_64BIT) || defined(CONFIG_KALLSYMS) 80 #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */ 81 #else 82 #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */ 83 #endif 84 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 85 86 #if CONFIG_PGTABLE_LEVELS == 3 87 #define PMD_TABLE_ORDER 1 88 #define PGD_TABLE_ORDER 0 89 #else 90 #define PGD_TABLE_ORDER 1 91 #endif 92 93 /* Definitions for 3rd level (we use PLD here for Page Lower directory 94 * because PTE_SHIFT is used lower down to mean shift that has to be 95 * done to get usable bits out of the PTE) */ 96 #define PLD_SHIFT PAGE_SHIFT 97 #define PLD_SIZE PAGE_SIZE 98 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 99 #define PTRS_PER_PTE (1UL << BITS_PER_PTE) 100 101 /* Definitions for 2nd level */ 102 #if CONFIG_PGTABLE_LEVELS == 3 103 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 104 #define PMD_SIZE (1UL << PMD_SHIFT) 105 #define PMD_MASK (~(PMD_SIZE-1)) 106 #define BITS_PER_PMD (PAGE_SHIFT + PMD_TABLE_ORDER - BITS_PER_PMD_ENTRY) 107 #define PTRS_PER_PMD (1UL << BITS_PER_PMD) 108 #else 109 #define BITS_PER_PMD 0 110 #endif 111 112 /* Definitions for 1st level */ 113 #define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD) 114 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG 115 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT) 116 #else 117 #define BITS_PER_PGD (PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY) 118 #endif 119 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 120 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 121 #define PTRS_PER_PGD (1UL << BITS_PER_PGD) 122 #define USER_PTRS_PER_PGD PTRS_PER_PGD 123 124 #ifdef CONFIG_64BIT 125 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 126 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 127 #define SPACEID_SHIFT (MAX_ADDRBITS - 32) 128 #else 129 #define MAX_ADDRBITS (BITS_PER_LONG) 130 #define MAX_ADDRESS (1ULL << MAX_ADDRBITS) 131 #define SPACEID_SHIFT 0 132 #endif 133 134 /* This calculates the number of initial pages we need for the initial 135 * page tables */ 136 #if (KERNEL_INITIAL_ORDER) >= (PLD_SHIFT + BITS_PER_PTE) 137 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PLD_SHIFT - BITS_PER_PTE)) 138 #else 139 # define PT_INITIAL (1) /* all initial PTEs fit into one page */ 140 #endif 141 142 /* 143 * pgd entries used up by user/kernel: 144 */ 145 146 /* NB: The tlb miss handlers make certain assumptions about the order */ 147 /* of the following bits, so be careful (One example, bits 25-31 */ 148 /* are moved together in one instruction). */ 149 150 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 151 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 152 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 153 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 154 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 155 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 156 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 157 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 158 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 159 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 160 #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */ 161 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 162 #ifdef CONFIG_HUGETLB_PAGE 163 #define _PAGE_SPECIAL_BIT _PAGE_DMB_BIT /* DMB feature is currently unused */ 164 #else 165 #define _PAGE_SPECIAL_BIT _PAGE_HPAGE_BIT /* use unused HUGE PAGE bit */ 166 #endif 167 168 /* N.B. The bits are defined in terms of a 32 bit word above, so the */ 169 /* following macro is ok for both 32 and 64 bit. */ 170 171 #define xlate_pabit(x) (31 - x) 172 173 /* this defines the shift to the usable bits in the PTE it is set so 174 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 175 * to zero */ 176 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 177 178 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 179 #define PFN_PTE_SHIFT 12 180 181 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 182 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 183 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 184 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 185 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 186 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 187 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 188 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 189 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 190 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 191 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 192 #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT)) 193 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 194 #define _PAGE_SPECIAL (1 << xlate_pabit(_PAGE_SPECIAL_BIT)) 195 196 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 197 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL) 198 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED) 199 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC) 200 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE) 201 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE) 202 203 /* We borrow bit 23 to store the exclusive marker in swap PTEs. */ 204 #define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED 205 206 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 207 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 208 * for a few meta-information bits, so we shift the address to be 209 * able to effectively address 40/42/44-bits of physical address space 210 * depending on 4k/16k/64k PAGE_SIZE */ 211 #define _PxD_PRESENT_BIT 31 212 #define _PxD_VALID_BIT 30 213 214 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 215 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 216 #define PxD_FLAG_MASK (0xf) 217 #define PxD_FLAG_SHIFT (4) 218 #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT) 219 220 #ifndef __ASSEMBLER__ 221 222 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER) 223 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE) 224 /* Others seem to make this executable, I don't know if that's correct 225 or not. The stack is mapped this way though so this is necessary 226 in the short term - dhd@linuxcare.com, 2000-08-08 */ 227 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ) 228 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE) 229 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC) 230 #define PAGE_COPY PAGE_EXECREAD 231 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 232 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 233 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC) 234 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX) 235 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO) 236 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 237 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ) 238 239 240 /* 241 * We could have an execute only page using "gateway - promote to priv 242 * level 3", but that is kind of silly. So, the way things are defined 243 * now, we must always have read permission for pages with execute 244 * permission. For the fun of it we'll go ahead and support write only 245 * pages. 246 */ 247 248 /*xwr*/ 249 250 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 251 252 /* initial page tables for 0-8MB for kernel */ 253 254 extern pte_t pg0[]; 255 256 #define pte_none(x) (pte_val(x) == 0) 257 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 258 #define pte_user(x) (pte_val(x) & _PAGE_USER) 259 #define pte_clear(mm, addr, xp) set_pte_at((mm), (addr), (xp), __pte(0)) 260 261 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 262 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 263 #define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK) 264 #define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 265 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 266 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 267 268 #define pmd_none(x) (!pmd_val(x)) 269 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 270 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 271 static inline void pmd_clear(pmd_t *pmd) { 272 set_pmd(pmd, __pmd(0)); 273 } 274 275 276 277 #if CONFIG_PGTABLE_LEVELS == 3 278 #define pud_pgtable(pud) ((pmd_t *) __va(pud_address(pud))) 279 #define pud_page(pud) virt_to_page((void *)pud_pgtable(pud)) 280 281 /* For 64 bit we have three level tables */ 282 283 #define pud_none(x) (!pud_val(x)) 284 #define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID)) 285 #define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT) 286 static inline void pud_clear(pud_t *pud) { 287 set_pud(pud, __pud(0)); 288 } 289 #endif 290 291 /* 292 * The following only work if pte_present() is true. 293 * Undefined behaviour if not.. 294 */ 295 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 296 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 297 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 298 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 299 300 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 301 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 302 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 303 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 304 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 305 static inline pte_t pte_mkwrite_novma(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 306 static inline pte_t pte_mkspecial(pte_t pte) { pte_val(pte) |= _PAGE_SPECIAL; return pte; } 307 308 /* 309 * Huge pte definitions. 310 */ 311 #ifdef CONFIG_HUGETLB_PAGE 312 #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE) 313 #define pte_mkhuge(pte) (__pte(pte_val(pte) | \ 314 (parisc_requires_coherency() ? 0 : _PAGE_HUGE))) 315 #else 316 #define pte_huge(pte) (0) 317 #define pte_mkhuge(pte) (pte) 318 #endif 319 320 321 #define __mk_pte(addr,pgprot) \ 322 ({ \ 323 pte_t __pte; \ 324 \ 325 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 326 \ 327 __pte; \ 328 }) 329 330 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 331 { 332 pte_t pte; 333 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 334 return pte; 335 } 336 337 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 338 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 339 340 /* Permanent address of a page. On parisc we don't have highmem. */ 341 342 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 343 344 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 345 346 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 347 { 348 return ((unsigned long) __va(pmd_address(pmd))); 349 } 350 351 #define pmd_pfn(pmd) (pmd_address(pmd) >> PAGE_SHIFT) 352 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 353 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 354 355 /* Find an entry in the second-level page table.. */ 356 357 extern void paging_init (void); 358 359 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 360 pte_t *ptep, pte_t pte, unsigned int nr) 361 { 362 if (pte_present(pte) && pte_user(pte)) 363 __update_cache(pte); 364 for (;;) { 365 *ptep = pte; 366 purge_tlb_entries(mm, addr); 367 if (--nr == 0) 368 break; 369 ptep++; 370 pte_val(pte) += 1 << PFN_PTE_SHIFT; 371 addr += PAGE_SIZE; 372 } 373 } 374 #define set_ptes set_ptes 375 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 376 377 /* Used for deferring calls to flush_dcache_page() */ 378 379 #define PG_dcache_dirty PG_arch_1 380 381 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) __update_cache(*ptep) 382 #define update_mmu_cache(vma, addr, ptep) __update_cache(*ptep) 383 384 /* 385 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 386 * are !pte_none() && !pte_present(). 387 * 388 * Format of swap PTEs (32bit): 389 * 390 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 391 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 392 * <---------------- offset -----------------> P E <ofs> < type -> 393 * 394 * E is the exclusive marker that is not stored in swap entries. 395 * _PAGE_PRESENT (P) must be 0. 396 * 397 * For the 64bit version, the offset is extended by 32bit. 398 */ 399 #define __swp_type(x) ((x).val & 0x1f) 400 #define __swp_offset(x) ( (((x).val >> 5) & 0x7) | \ 401 (((x).val >> 10) << 3) ) 402 #define __swp_entry(type, offset) ((swp_entry_t) { \ 403 ((type) & 0x1f) | \ 404 ((offset & 0x7) << 5) | \ 405 ((offset >> 3) << 10) }) 406 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 407 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 408 409 static inline bool pte_swp_exclusive(pte_t pte) 410 { 411 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 412 } 413 414 static inline pte_t pte_swp_mkexclusive(pte_t pte) 415 { 416 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; 417 return pte; 418 } 419 420 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 421 { 422 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; 423 return pte; 424 } 425 426 static inline pte_t ptep_get(pte_t *ptep) 427 { 428 return READ_ONCE(*ptep); 429 } 430 #define ptep_get ptep_get 431 432 static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma, 433 unsigned long addr, pte_t *ptep) 434 { 435 pte_t pte; 436 437 pte = ptep_get(ptep); 438 if (!pte_young(pte)) { 439 return false; 440 } 441 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 442 return true; 443 } 444 445 bool ptep_clear_flush_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep); 446 pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep); 447 448 struct mm_struct; 449 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 450 { 451 set_pte_at(mm, addr, ptep, pte_wrprotect(*ptep)); 452 } 453 454 #define pte_same(A,B) (pte_val(A) == pte_val(B)) 455 456 #endif /* !__ASSEMBLER__ */ 457 458 459 /* TLB page size encoding - see table 3-1 in parisc20.pdf */ 460 #define _PAGE_SIZE_ENCODING_4K 0 461 #define _PAGE_SIZE_ENCODING_16K 1 462 #define _PAGE_SIZE_ENCODING_64K 2 463 #define _PAGE_SIZE_ENCODING_256K 3 464 #define _PAGE_SIZE_ENCODING_1M 4 465 #define _PAGE_SIZE_ENCODING_4M 5 466 #define _PAGE_SIZE_ENCODING_16M 6 467 #define _PAGE_SIZE_ENCODING_64M 7 468 469 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 470 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 471 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 472 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 473 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 474 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 475 #endif 476 477 478 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 479 480 /* We provide our own get_unmapped_area to provide cache coherency */ 481 482 #define HAVE_ARCH_UNMAPPED_AREA 483 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 484 485 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 486 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 487 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 488 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 489 #define __HAVE_ARCH_PTE_SAME 490 491 #endif /* _PARISC_PGTABLE_H */ 492