1*deae26bfSKyle McMartin #ifndef __ASM_PARISC_PCI_H 2*deae26bfSKyle McMartin #define __ASM_PARISC_PCI_H 3*deae26bfSKyle McMartin 4*deae26bfSKyle McMartin #include <asm/scatterlist.h> 5*deae26bfSKyle McMartin 6*deae26bfSKyle McMartin 7*deae26bfSKyle McMartin 8*deae26bfSKyle McMartin /* 9*deae26bfSKyle McMartin ** HP PCI platforms generally support multiple bus adapters. 10*deae26bfSKyle McMartin ** (workstations 1-~4, servers 2-~32) 11*deae26bfSKyle McMartin ** 12*deae26bfSKyle McMartin ** Newer platforms number the busses across PCI bus adapters *sparsely*. 13*deae26bfSKyle McMartin ** E.g. 0, 8, 16, ... 14*deae26bfSKyle McMartin ** 15*deae26bfSKyle McMartin ** Under a PCI bus, most HP platforms support PPBs up to two or three 16*deae26bfSKyle McMartin ** levels deep. See "Bit3" product line. 17*deae26bfSKyle McMartin */ 18*deae26bfSKyle McMartin #define PCI_MAX_BUSSES 256 19*deae26bfSKyle McMartin 20*deae26bfSKyle McMartin 21*deae26bfSKyle McMartin /* To be used as: mdelay(pci_post_reset_delay); 22*deae26bfSKyle McMartin * 23*deae26bfSKyle McMartin * post_reset is the time the kernel should stall to prevent anyone from 24*deae26bfSKyle McMartin * accessing the PCI bus once #RESET is de-asserted. 25*deae26bfSKyle McMartin * PCI spec somewhere says 1 second but with multi-PCI bus systems, 26*deae26bfSKyle McMartin * this makes the boot time much longer than necessary. 27*deae26bfSKyle McMartin * 20ms seems to work for all the HP PCI implementations to date. 28*deae26bfSKyle McMartin */ 29*deae26bfSKyle McMartin #define pci_post_reset_delay 50 30*deae26bfSKyle McMartin 31*deae26bfSKyle McMartin 32*deae26bfSKyle McMartin /* 33*deae26bfSKyle McMartin ** pci_hba_data (aka H2P_OBJECT in HP/UX) 34*deae26bfSKyle McMartin ** 35*deae26bfSKyle McMartin ** This is the "common" or "base" data structure which HBA drivers 36*deae26bfSKyle McMartin ** (eg Dino or LBA) are required to place at the top of their own 37*deae26bfSKyle McMartin ** platform_data structure. I've heard this called "C inheritance" too. 38*deae26bfSKyle McMartin ** 39*deae26bfSKyle McMartin ** Data needed by pcibios layer belongs here. 40*deae26bfSKyle McMartin */ 41*deae26bfSKyle McMartin struct pci_hba_data { 42*deae26bfSKyle McMartin void __iomem *base_addr; /* aka Host Physical Address */ 43*deae26bfSKyle McMartin const struct parisc_device *dev; /* device from PA bus walk */ 44*deae26bfSKyle McMartin struct pci_bus *hba_bus; /* primary PCI bus below HBA */ 45*deae26bfSKyle McMartin int hba_num; /* I/O port space access "key" */ 46*deae26bfSKyle McMartin struct resource bus_num; /* PCI bus numbers */ 47*deae26bfSKyle McMartin struct resource io_space; /* PIOP */ 48*deae26bfSKyle McMartin struct resource lmmio_space; /* bus addresses < 4Gb */ 49*deae26bfSKyle McMartin struct resource elmmio_space; /* additional bus addresses < 4Gb */ 50*deae26bfSKyle McMartin struct resource gmmio_space; /* bus addresses > 4Gb */ 51*deae26bfSKyle McMartin 52*deae26bfSKyle McMartin /* NOTE: Dino code assumes it can use *all* of the lmmio_space, 53*deae26bfSKyle McMartin * elmmio_space and gmmio_space as a contiguous array of 54*deae26bfSKyle McMartin * resources. This #define represents the array size */ 55*deae26bfSKyle McMartin #define DINO_MAX_LMMIO_RESOURCES 3 56*deae26bfSKyle McMartin 57*deae26bfSKyle McMartin unsigned long lmmio_space_offset; /* CPU view - PCI view */ 58*deae26bfSKyle McMartin void * iommu; /* IOMMU this device is under */ 59*deae26bfSKyle McMartin /* REVISIT - spinlock to protect resources? */ 60*deae26bfSKyle McMartin 61*deae26bfSKyle McMartin #define HBA_NAME_SIZE 16 62*deae26bfSKyle McMartin char io_name[HBA_NAME_SIZE]; 63*deae26bfSKyle McMartin char lmmio_name[HBA_NAME_SIZE]; 64*deae26bfSKyle McMartin char elmmio_name[HBA_NAME_SIZE]; 65*deae26bfSKyle McMartin char gmmio_name[HBA_NAME_SIZE]; 66*deae26bfSKyle McMartin }; 67*deae26bfSKyle McMartin 68*deae26bfSKyle McMartin #define HBA_DATA(d) ((struct pci_hba_data *) (d)) 69*deae26bfSKyle McMartin 70*deae26bfSKyle McMartin /* 71*deae26bfSKyle McMartin ** We support 2^16 I/O ports per HBA. These are set up in the form 72*deae26bfSKyle McMartin ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port 73*deae26bfSKyle McMartin ** space address. 74*deae26bfSKyle McMartin */ 75*deae26bfSKyle McMartin #define HBA_PORT_SPACE_BITS 16 76*deae26bfSKyle McMartin 77*deae26bfSKyle McMartin #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) 78*deae26bfSKyle McMartin #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) 79*deae26bfSKyle McMartin 80*deae26bfSKyle McMartin #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) 81*deae26bfSKyle McMartin #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) 82*deae26bfSKyle McMartin 83*deae26bfSKyle McMartin #ifdef CONFIG_64BIT 84*deae26bfSKyle McMartin #define PCI_F_EXTEND 0xffffffff00000000UL 85*deae26bfSKyle McMartin #define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a) 86*deae26bfSKyle McMartin 87*deae26bfSKyle McMartin /* We need to know if an address is LMMMIO or GMMIO. 88*deae26bfSKyle McMartin * LMMIO requires mangling and GMMIO we must use as-is. 89*deae26bfSKyle McMartin */ 90*deae26bfSKyle McMartin static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a) 91*deae26bfSKyle McMartin { 92*deae26bfSKyle McMartin return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND); 93*deae26bfSKyle McMartin } 94*deae26bfSKyle McMartin 95*deae26bfSKyle McMartin /* 96*deae26bfSKyle McMartin ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses. 97*deae26bfSKyle McMartin ** See pci.c for more conversions used by Generic PCI code. 98*deae26bfSKyle McMartin ** 99*deae26bfSKyle McMartin ** Platform characteristics/firmware guarantee that 100*deae26bfSKyle McMartin ** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO 101*deae26bfSKyle McMartin ** (2) PA_VIEW == IO_VIEW for GMMIO 102*deae26bfSKyle McMartin */ 103*deae26bfSKyle McMartin #define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \ 104*deae26bfSKyle McMartin ? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \ 105*deae26bfSKyle McMartin : (a)) /* GMMIO */ 106*deae26bfSKyle McMartin #define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \ 107*deae26bfSKyle McMartin ? (a) + hba->lmmio_space_offset \ 108*deae26bfSKyle McMartin : (a)) 109*deae26bfSKyle McMartin 110*deae26bfSKyle McMartin #else /* !CONFIG_64BIT */ 111*deae26bfSKyle McMartin 112*deae26bfSKyle McMartin #define PCI_BUS_ADDR(hba,a) (a) 113*deae26bfSKyle McMartin #define PCI_HOST_ADDR(hba,a) (a) 114*deae26bfSKyle McMartin #define PCI_F_EXTEND 0UL 115*deae26bfSKyle McMartin #define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */ 116*deae26bfSKyle McMartin 117*deae26bfSKyle McMartin #endif /* !CONFIG_64BIT */ 118*deae26bfSKyle McMartin 119*deae26bfSKyle McMartin /* 120*deae26bfSKyle McMartin ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus 121*deae26bfSKyle McMartin ** (This eliminates some of the warnings). 122*deae26bfSKyle McMartin */ 123*deae26bfSKyle McMartin struct pci_bus; 124*deae26bfSKyle McMartin struct pci_dev; 125*deae26bfSKyle McMartin 126*deae26bfSKyle McMartin /* 127*deae26bfSKyle McMartin * If the PCI device's view of memory is the same as the CPU's view of memory, 128*deae26bfSKyle McMartin * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use 129*deae26bfSKyle McMartin * this boolean for bounce buffer decisions. 130*deae26bfSKyle McMartin */ 131*deae26bfSKyle McMartin #ifdef CONFIG_PA20 132*deae26bfSKyle McMartin /* All PA-2.0 machines have an IOMMU. */ 133*deae26bfSKyle McMartin #define PCI_DMA_BUS_IS_PHYS 0 134*deae26bfSKyle McMartin #define parisc_has_iommu() do { } while (0) 135*deae26bfSKyle McMartin #else 136*deae26bfSKyle McMartin 137*deae26bfSKyle McMartin #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) 138*deae26bfSKyle McMartin extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ 139*deae26bfSKyle McMartin #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys 140*deae26bfSKyle McMartin #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) 141*deae26bfSKyle McMartin #else 142*deae26bfSKyle McMartin #define PCI_DMA_BUS_IS_PHYS 1 143*deae26bfSKyle McMartin #define parisc_has_iommu() do { } while (0) 144*deae26bfSKyle McMartin #endif 145*deae26bfSKyle McMartin 146*deae26bfSKyle McMartin #endif /* !CONFIG_PA20 */ 147*deae26bfSKyle McMartin 148*deae26bfSKyle McMartin 149*deae26bfSKyle McMartin /* 150*deae26bfSKyle McMartin ** Most PCI devices (eg Tulip, NCR720) also export the same registers 151*deae26bfSKyle McMartin ** to both MMIO and I/O port space. Due to poor performance of I/O Port 152*deae26bfSKyle McMartin ** access under HP PCI bus adapters, strongly recommend the use of MMIO 153*deae26bfSKyle McMartin ** address space. 154*deae26bfSKyle McMartin ** 155*deae26bfSKyle McMartin ** While I'm at it more PA programming notes: 156*deae26bfSKyle McMartin ** 157*deae26bfSKyle McMartin ** 1) MMIO stores (writes) are posted operations. This means the processor 158*deae26bfSKyle McMartin ** gets an "ACK" before the write actually gets to the device. A read 159*deae26bfSKyle McMartin ** to the same device (or typically the bus adapter above it) will 160*deae26bfSKyle McMartin ** force in-flight write transaction(s) out to the targeted device 161*deae26bfSKyle McMartin ** before the read can complete. 162*deae26bfSKyle McMartin ** 163*deae26bfSKyle McMartin ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with 164*deae26bfSKyle McMartin ** respect to DMA on all platforms. Ie PIO data can reach the processor 165*deae26bfSKyle McMartin ** before in-flight DMA reaches memory. Since most SMP PA platforms 166*deae26bfSKyle McMartin ** are I/O coherent, it generally doesn't matter...but sometimes 167*deae26bfSKyle McMartin ** it does. 168*deae26bfSKyle McMartin ** 169*deae26bfSKyle McMartin ** I've helped device driver writers debug both types of problems. 170*deae26bfSKyle McMartin */ 171*deae26bfSKyle McMartin struct pci_port_ops { 172*deae26bfSKyle McMartin u8 (*inb) (struct pci_hba_data *hba, u16 port); 173*deae26bfSKyle McMartin u16 (*inw) (struct pci_hba_data *hba, u16 port); 174*deae26bfSKyle McMartin u32 (*inl) (struct pci_hba_data *hba, u16 port); 175*deae26bfSKyle McMartin void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); 176*deae26bfSKyle McMartin void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); 177*deae26bfSKyle McMartin void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); 178*deae26bfSKyle McMartin }; 179*deae26bfSKyle McMartin 180*deae26bfSKyle McMartin 181*deae26bfSKyle McMartin struct pci_bios_ops { 182*deae26bfSKyle McMartin void (*init)(void); 183*deae26bfSKyle McMartin void (*fixup_bus)(struct pci_bus *bus); 184*deae26bfSKyle McMartin }; 185*deae26bfSKyle McMartin 186*deae26bfSKyle McMartin /* pci_unmap_{single,page} is not a nop, thus... */ 187*deae26bfSKyle McMartin #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 188*deae26bfSKyle McMartin dma_addr_t ADDR_NAME; 189*deae26bfSKyle McMartin #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 190*deae26bfSKyle McMartin __u32 LEN_NAME; 191*deae26bfSKyle McMartin #define pci_unmap_addr(PTR, ADDR_NAME) \ 192*deae26bfSKyle McMartin ((PTR)->ADDR_NAME) 193*deae26bfSKyle McMartin #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 194*deae26bfSKyle McMartin (((PTR)->ADDR_NAME) = (VAL)) 195*deae26bfSKyle McMartin #define pci_unmap_len(PTR, LEN_NAME) \ 196*deae26bfSKyle McMartin ((PTR)->LEN_NAME) 197*deae26bfSKyle McMartin #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 198*deae26bfSKyle McMartin (((PTR)->LEN_NAME) = (VAL)) 199*deae26bfSKyle McMartin 200*deae26bfSKyle McMartin /* 201*deae26bfSKyle McMartin ** Stuff declared in arch/parisc/kernel/pci.c 202*deae26bfSKyle McMartin */ 203*deae26bfSKyle McMartin extern struct pci_port_ops *pci_port; 204*deae26bfSKyle McMartin extern struct pci_bios_ops *pci_bios; 205*deae26bfSKyle McMartin 206*deae26bfSKyle McMartin #ifdef CONFIG_PCI 207*deae26bfSKyle McMartin extern void pcibios_register_hba(struct pci_hba_data *); 208*deae26bfSKyle McMartin extern void pcibios_set_master(struct pci_dev *); 209*deae26bfSKyle McMartin #else 210*deae26bfSKyle McMartin static inline void pcibios_register_hba(struct pci_hba_data *x) 211*deae26bfSKyle McMartin { 212*deae26bfSKyle McMartin } 213*deae26bfSKyle McMartin #endif 214*deae26bfSKyle McMartin 215*deae26bfSKyle McMartin /* 216*deae26bfSKyle McMartin * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() 217*deae26bfSKyle McMartin * 0 == check if bridge is numbered before re-numbering. 218*deae26bfSKyle McMartin * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. 219*deae26bfSKyle McMartin * 220*deae26bfSKyle McMartin * We *should* set this to zero for "legacy" platforms and one 221*deae26bfSKyle McMartin * for PAT platforms. 222*deae26bfSKyle McMartin * 223*deae26bfSKyle McMartin * But legacy platforms also need to renumber the busses below a Host 224*deae26bfSKyle McMartin * Bus controller. Adding a 4-port Tulip card on the first PCI root 225*deae26bfSKyle McMartin * bus of a C200 resulted in the secondary bus being numbered as 1. 226*deae26bfSKyle McMartin * The second PCI host bus controller's root bus had already been 227*deae26bfSKyle McMartin * assigned bus number 1 by firmware and sysfs complained. 228*deae26bfSKyle McMartin * 229*deae26bfSKyle McMartin * Firmware isn't doing anything wrong here since each controller 230*deae26bfSKyle McMartin * is its own PCI domain. It's simpler and easier for us to renumber 231*deae26bfSKyle McMartin * the busses rather than treat each Dino as a separate PCI domain. 232*deae26bfSKyle McMartin * Eventually, we may want to introduce PCI domains for Superdome or 233*deae26bfSKyle McMartin * rp7420/8420 boxes and then revisit this issue. 234*deae26bfSKyle McMartin */ 235*deae26bfSKyle McMartin #define pcibios_assign_all_busses() (1) 236*deae26bfSKyle McMartin #define pcibios_scan_all_fns(a, b) (0) 237*deae26bfSKyle McMartin 238*deae26bfSKyle McMartin #define PCIBIOS_MIN_IO 0x10 239*deae26bfSKyle McMartin #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ 240*deae26bfSKyle McMartin 241*deae26bfSKyle McMartin /* export the pci_ DMA API in terms of the dma_ one */ 242*deae26bfSKyle McMartin #include <asm-generic/pci-dma-compat.h> 243*deae26bfSKyle McMartin 244*deae26bfSKyle McMartin #ifdef CONFIG_PCI 245*deae26bfSKyle McMartin static inline void pci_dma_burst_advice(struct pci_dev *pdev, 246*deae26bfSKyle McMartin enum pci_dma_burst_strategy *strat, 247*deae26bfSKyle McMartin unsigned long *strategy_parameter) 248*deae26bfSKyle McMartin { 249*deae26bfSKyle McMartin unsigned long cacheline_size; 250*deae26bfSKyle McMartin u8 byte; 251*deae26bfSKyle McMartin 252*deae26bfSKyle McMartin pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 253*deae26bfSKyle McMartin if (byte == 0) 254*deae26bfSKyle McMartin cacheline_size = 1024; 255*deae26bfSKyle McMartin else 256*deae26bfSKyle McMartin cacheline_size = (int) byte * 4; 257*deae26bfSKyle McMartin 258*deae26bfSKyle McMartin *strat = PCI_DMA_BURST_MULTIPLE; 259*deae26bfSKyle McMartin *strategy_parameter = cacheline_size; 260*deae26bfSKyle McMartin } 261*deae26bfSKyle McMartin #endif 262*deae26bfSKyle McMartin 263*deae26bfSKyle McMartin extern void 264*deae26bfSKyle McMartin pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 265*deae26bfSKyle McMartin struct resource *res); 266*deae26bfSKyle McMartin 267*deae26bfSKyle McMartin extern void 268*deae26bfSKyle McMartin pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 269*deae26bfSKyle McMartin struct pci_bus_region *region); 270*deae26bfSKyle McMartin 271*deae26bfSKyle McMartin static inline struct resource * 272*deae26bfSKyle McMartin pcibios_select_root(struct pci_dev *pdev, struct resource *res) 273*deae26bfSKyle McMartin { 274*deae26bfSKyle McMartin struct resource *root = NULL; 275*deae26bfSKyle McMartin 276*deae26bfSKyle McMartin if (res->flags & IORESOURCE_IO) 277*deae26bfSKyle McMartin root = &ioport_resource; 278*deae26bfSKyle McMartin if (res->flags & IORESOURCE_MEM) 279*deae26bfSKyle McMartin root = &iomem_resource; 280*deae26bfSKyle McMartin 281*deae26bfSKyle McMartin return root; 282*deae26bfSKyle McMartin } 283*deae26bfSKyle McMartin 284*deae26bfSKyle McMartin static inline void pcibios_penalize_isa_irq(int irq, int active) 285*deae26bfSKyle McMartin { 286*deae26bfSKyle McMartin /* We don't need to penalize isa irq's */ 287*deae26bfSKyle McMartin } 288*deae26bfSKyle McMartin 289*deae26bfSKyle McMartin static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 290*deae26bfSKyle McMartin { 291*deae26bfSKyle McMartin return channel ? 15 : 14; 292*deae26bfSKyle McMartin } 293*deae26bfSKyle McMartin 294*deae26bfSKyle McMartin #endif /* __ASM_PARISC_PCI_H */ 295