1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2deae26bfSKyle McMartin #ifndef __ASM_PARISC_PCI_H
3deae26bfSKyle McMartin #define __ASM_PARISC_PCI_H
4deae26bfSKyle McMartin
584be456fSChristoph Hellwig #include <linux/scatterlist.h>
6deae26bfSKyle McMartin
7deae26bfSKyle McMartin
8deae26bfSKyle McMartin
9deae26bfSKyle McMartin /*
10deae26bfSKyle McMartin ** HP PCI platforms generally support multiple bus adapters.
11deae26bfSKyle McMartin ** (workstations 1-~4, servers 2-~32)
12deae26bfSKyle McMartin **
13deae26bfSKyle McMartin ** Newer platforms number the busses across PCI bus adapters *sparsely*.
14deae26bfSKyle McMartin ** E.g. 0, 8, 16, ...
15deae26bfSKyle McMartin **
16deae26bfSKyle McMartin ** Under a PCI bus, most HP platforms support PPBs up to two or three
17deae26bfSKyle McMartin ** levels deep. See "Bit3" product line.
18deae26bfSKyle McMartin */
19deae26bfSKyle McMartin #define PCI_MAX_BUSSES 256
20deae26bfSKyle McMartin
21deae26bfSKyle McMartin
22deae26bfSKyle McMartin /* To be used as: mdelay(pci_post_reset_delay);
23deae26bfSKyle McMartin *
24deae26bfSKyle McMartin * post_reset is the time the kernel should stall to prevent anyone from
25deae26bfSKyle McMartin * accessing the PCI bus once #RESET is de-asserted.
26deae26bfSKyle McMartin * PCI spec somewhere says 1 second but with multi-PCI bus systems,
27deae26bfSKyle McMartin * this makes the boot time much longer than necessary.
28deae26bfSKyle McMartin * 20ms seems to work for all the HP PCI implementations to date.
29deae26bfSKyle McMartin */
30deae26bfSKyle McMartin #define pci_post_reset_delay 50
31deae26bfSKyle McMartin
32deae26bfSKyle McMartin
33deae26bfSKyle McMartin /*
34deae26bfSKyle McMartin ** pci_hba_data (aka H2P_OBJECT in HP/UX)
35deae26bfSKyle McMartin **
36deae26bfSKyle McMartin ** This is the "common" or "base" data structure which HBA drivers
37deae26bfSKyle McMartin ** (eg Dino or LBA) are required to place at the top of their own
38deae26bfSKyle McMartin ** platform_data structure. I've heard this called "C inheritance" too.
39deae26bfSKyle McMartin **
40deae26bfSKyle McMartin ** Data needed by pcibios layer belongs here.
41deae26bfSKyle McMartin */
42deae26bfSKyle McMartin struct pci_hba_data {
43deae26bfSKyle McMartin void __iomem *base_addr; /* aka Host Physical Address */
44deae26bfSKyle McMartin const struct parisc_device *dev; /* device from PA bus walk */
45deae26bfSKyle McMartin struct pci_bus *hba_bus; /* primary PCI bus below HBA */
46deae26bfSKyle McMartin int hba_num; /* I/O port space access "key" */
47deae26bfSKyle McMartin struct resource bus_num; /* PCI bus numbers */
48deae26bfSKyle McMartin struct resource io_space; /* PIOP */
49deae26bfSKyle McMartin struct resource lmmio_space; /* bus addresses < 4Gb */
50deae26bfSKyle McMartin struct resource elmmio_space; /* additional bus addresses < 4Gb */
51deae26bfSKyle McMartin struct resource gmmio_space; /* bus addresses > 4Gb */
52deae26bfSKyle McMartin
53deae26bfSKyle McMartin /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
54deae26bfSKyle McMartin * elmmio_space and gmmio_space as a contiguous array of
55deae26bfSKyle McMartin * resources. This #define represents the array size */
56deae26bfSKyle McMartin #define DINO_MAX_LMMIO_RESOURCES 3
57deae26bfSKyle McMartin
58deae26bfSKyle McMartin unsigned long lmmio_space_offset; /* CPU view - PCI view */
59*79b428daSChristoph Hellwig struct ioc *iommu; /* IOMMU this device is under */
60deae26bfSKyle McMartin /* REVISIT - spinlock to protect resources? */
61deae26bfSKyle McMartin
62deae26bfSKyle McMartin #define HBA_NAME_SIZE 16
63deae26bfSKyle McMartin char io_name[HBA_NAME_SIZE];
64deae26bfSKyle McMartin char lmmio_name[HBA_NAME_SIZE];
65deae26bfSKyle McMartin char elmmio_name[HBA_NAME_SIZE];
66deae26bfSKyle McMartin char gmmio_name[HBA_NAME_SIZE];
67deae26bfSKyle McMartin };
68deae26bfSKyle McMartin
69deae26bfSKyle McMartin /*
70deae26bfSKyle McMartin ** We support 2^16 I/O ports per HBA. These are set up in the form
71deae26bfSKyle McMartin ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
72deae26bfSKyle McMartin ** space address.
73deae26bfSKyle McMartin */
74deae26bfSKyle McMartin #define HBA_PORT_SPACE_BITS 16
75deae26bfSKyle McMartin
76deae26bfSKyle McMartin #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
77deae26bfSKyle McMartin #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
78deae26bfSKyle McMartin
79deae26bfSKyle McMartin #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
80deae26bfSKyle McMartin #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
81deae26bfSKyle McMartin
82deae26bfSKyle McMartin #ifdef CONFIG_64BIT
83deae26bfSKyle McMartin #define PCI_F_EXTEND 0xffffffff00000000UL
84deae26bfSKyle McMartin #else /* !CONFIG_64BIT */
85deae26bfSKyle McMartin #define PCI_F_EXTEND 0UL
86deae26bfSKyle McMartin #endif /* !CONFIG_64BIT */
87deae26bfSKyle McMartin
88deae26bfSKyle McMartin /*
89deae26bfSKyle McMartin ** Most PCI devices (eg Tulip, NCR720) also export the same registers
90deae26bfSKyle McMartin ** to both MMIO and I/O port space. Due to poor performance of I/O Port
91deae26bfSKyle McMartin ** access under HP PCI bus adapters, strongly recommend the use of MMIO
92deae26bfSKyle McMartin ** address space.
93deae26bfSKyle McMartin **
94deae26bfSKyle McMartin ** While I'm at it more PA programming notes:
95deae26bfSKyle McMartin **
96deae26bfSKyle McMartin ** 1) MMIO stores (writes) are posted operations. This means the processor
97deae26bfSKyle McMartin ** gets an "ACK" before the write actually gets to the device. A read
98deae26bfSKyle McMartin ** to the same device (or typically the bus adapter above it) will
99deae26bfSKyle McMartin ** force in-flight write transaction(s) out to the targeted device
100deae26bfSKyle McMartin ** before the read can complete.
101deae26bfSKyle McMartin **
102deae26bfSKyle McMartin ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
103deae26bfSKyle McMartin ** respect to DMA on all platforms. Ie PIO data can reach the processor
104deae26bfSKyle McMartin ** before in-flight DMA reaches memory. Since most SMP PA platforms
105deae26bfSKyle McMartin ** are I/O coherent, it generally doesn't matter...but sometimes
106deae26bfSKyle McMartin ** it does.
107deae26bfSKyle McMartin **
108deae26bfSKyle McMartin ** I've helped device driver writers debug both types of problems.
109deae26bfSKyle McMartin */
110deae26bfSKyle McMartin struct pci_port_ops {
111deae26bfSKyle McMartin u8 (*inb) (struct pci_hba_data *hba, u16 port);
112deae26bfSKyle McMartin u16 (*inw) (struct pci_hba_data *hba, u16 port);
113deae26bfSKyle McMartin u32 (*inl) (struct pci_hba_data *hba, u16 port);
114deae26bfSKyle McMartin void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
115deae26bfSKyle McMartin void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
116deae26bfSKyle McMartin void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
117deae26bfSKyle McMartin };
118deae26bfSKyle McMartin
119deae26bfSKyle McMartin
120deae26bfSKyle McMartin struct pci_bios_ops {
121deae26bfSKyle McMartin void (*init)(void);
122deae26bfSKyle McMartin void (*fixup_bus)(struct pci_bus *bus);
123deae26bfSKyle McMartin };
124deae26bfSKyle McMartin
125deae26bfSKyle McMartin /*
126deae26bfSKyle McMartin ** Stuff declared in arch/parisc/kernel/pci.c
127deae26bfSKyle McMartin */
128deae26bfSKyle McMartin extern struct pci_port_ops *pci_port;
129deae26bfSKyle McMartin extern struct pci_bios_ops *pci_bios;
130deae26bfSKyle McMartin
131deae26bfSKyle McMartin #ifdef CONFIG_PCI
132deae26bfSKyle McMartin extern void pcibios_register_hba(struct pci_hba_data *);
133deae26bfSKyle McMartin #else
pcibios_register_hba(struct pci_hba_data * x)134deae26bfSKyle McMartin static inline void pcibios_register_hba(struct pci_hba_data *x)
135deae26bfSKyle McMartin {
136deae26bfSKyle McMartin }
137deae26bfSKyle McMartin #endif
138602c9c9aSHelge Deller extern void pcibios_init_bridge(struct pci_dev *);
139deae26bfSKyle McMartin
140deae26bfSKyle McMartin /*
141deae26bfSKyle McMartin * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
142deae26bfSKyle McMartin * 0 == check if bridge is numbered before re-numbering.
143deae26bfSKyle McMartin * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
144deae26bfSKyle McMartin *
145deae26bfSKyle McMartin * We *should* set this to zero for "legacy" platforms and one
146deae26bfSKyle McMartin * for PAT platforms.
147deae26bfSKyle McMartin *
148deae26bfSKyle McMartin * But legacy platforms also need to renumber the busses below a Host
149deae26bfSKyle McMartin * Bus controller. Adding a 4-port Tulip card on the first PCI root
150deae26bfSKyle McMartin * bus of a C200 resulted in the secondary bus being numbered as 1.
151deae26bfSKyle McMartin * The second PCI host bus controller's root bus had already been
152deae26bfSKyle McMartin * assigned bus number 1 by firmware and sysfs complained.
153deae26bfSKyle McMartin *
154deae26bfSKyle McMartin * Firmware isn't doing anything wrong here since each controller
155deae26bfSKyle McMartin * is its own PCI domain. It's simpler and easier for us to renumber
156deae26bfSKyle McMartin * the busses rather than treat each Dino as a separate PCI domain.
157deae26bfSKyle McMartin * Eventually, we may want to introduce PCI domains for Superdome or
158deae26bfSKyle McMartin * rp7420/8420 boxes and then revisit this issue.
159deae26bfSKyle McMartin */
160deae26bfSKyle McMartin #define pcibios_assign_all_busses() (1)
161deae26bfSKyle McMartin
162deae26bfSKyle McMartin #define PCIBIOS_MIN_IO 0x10
163deae26bfSKyle McMartin #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
164deae26bfSKyle McMartin
1652cc7138fSThomas Bogendoerfer #define HAVE_PCI_MMAP
1666a94ca14SDavid Woodhouse #define ARCH_GENERIC_PCI_MMAP_RESOURCE
1672cc7138fSThomas Bogendoerfer
168deae26bfSKyle McMartin #endif /* __ASM_PARISC_PCI_H */
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