1 #ifndef _ASM_HASH_H 2 #define _ASM_HASH_H 3 4 /* 5 * HP-PA only implements integer multiply in the FPU. However, for 6 * integer multiplies by constant, it has a number of shift-and-add 7 * (but no shift-and-subtract, sigh!) instructions that a compiler 8 * can synthesize a code sequence with. 9 * 10 * Unfortunately, GCC isn't very efficient at using them. For example 11 * it uses three instructions for "x *= 21" when only two are needed. 12 * But we can find a sequence manually. 13 */ 14 15 #define HAVE_ARCH__HASH_32 1 16 17 /* 18 * This is a multiply by GOLDEN_RATIO_32 = 0x61C88647 optimized for the 19 * PA7100 pairing rules. This is an in-order 2-way superscalar processor. 20 * Only one instruction in a pair may be a shift (by more than 3 bits), 21 * but other than that, simple ALU ops (including shift-and-add by up 22 * to 3 bits) may be paired arbitrarily. 23 * 24 * PA8xxx processors also dual-issue ALU instructions, although with 25 * fewer constraints, so this schedule is good for them, too. 26 * 27 * This 6-step sequence was found by Yevgen Voronenko's implementation 28 * of the Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html. 29 */ 30 static inline u32 __attribute_const__ __hash_32(u32 x) 31 { 32 u32 a, b, c; 33 34 /* 35 * Phase 1: Compute a = (x << 19) + x, 36 * b = (x << 9) + a, c = (x << 23) + b. 37 */ 38 a = x << 19; /* Two shifts can't be paired */ 39 b = x << 9; a += x; 40 c = x << 23; b += a; 41 c += b; 42 /* Phase 2: Return (b<<11) + (c<<6) + (a<<3) - c */ 43 b <<= 11; 44 a += c << 3; b -= c; 45 return (a << 3) + b; 46 } 47 48 #if BITS_PER_LONG == 64 49 50 #define HAVE_ARCH_HASH_64 1 51 52 /* 53 * Finding a good shift-and-add chain for GOLDEN_RATIO_64 is tricky, 54 * because available software for the purpose chokes on constants this 55 * large. (It's mostly designed for compiling FIR filter coefficients 56 * into FPGAs.) 57 * 58 * However, Jason Thong pointed out a work-around. The Hcub software 59 * (http://spiral.ece.cmu.edu/mcm/gen.html) is designed for *multiple* 60 * constant multiplication, and is good at finding shift-and-add chains 61 * which share common terms. 62 * 63 * Looking at 0x0x61C8864680B583EB in binary: 64 * 0110000111001000100001100100011010000000101101011000001111101011 65 * \______________/ \__________/ \_______/ \________/ 66 * \____________________________/ \____________________/ 67 * you can see the non-zero bits are divided into several well-separated 68 * blocks. Hcub can find algorithms for those terms separately, which 69 * can then be shifted and added together. 70 * 71 * Dividing the input into 2, 3 or 4 blocks, Hcub can find solutions 72 * with 10, 9 or 8 adds, respectively, making a total of 11 for the 73 * whole number. 74 * 75 * Using just two large blocks, 0xC3910C8D << 31 in the high bits, 76 * and 0xB583EB in the low bits, produces as good an algorithm as any, 77 * and with one more small shift than alternatives. 78 * 79 * The high bits are a larger number and more work to compute, as well 80 * as needing one extra cycle to shift left 31 bits before the final 81 * addition, so they are the critical path for scheduling. The low bits 82 * can fit into the scheduling slots left over. 83 */ 84 85 86 /* 87 * This _ASSIGN(dst, src) macro performs "dst = src", but prevents GCC 88 * from inferring anything about the value assigned to "dest". 89 * 90 * This prevents it from mis-optimizing certain sequences. 91 * In particular, gcc is annoyingly eager to combine consecutive shifts. 92 * Given "x <<= 19; y += x; z += x << 1;", GCC will turn this into 93 * "y += x << 19; z += x << 20;" even though the latter sequence needs 94 * an additional instruction and temporary register. 95 * 96 * Because no actual assembly code is generated, this construct is 97 * usefully portable across all GCC platforms, and so can be test-compiled 98 * on non-PA systems. 99 * 100 * In two places, additional unused input dependencies are added. This 101 * forces GCC's scheduling so it does not rearrange instructions too much. 102 * Because the PA-8xxx is out of order, I'm not sure how much this matters, 103 * but why make it more difficult for the processor than necessary? 104 */ 105 #define _ASSIGN(dst, src, ...) asm("" : "=r" (dst) : "0" (src), ##__VA_ARGS__) 106 107 /* 108 * Multiply by GOLDEN_RATIO_64 = 0x0x61C8864680B583EB using a heavily 109 * optimized shift-and-add sequence. 110 * 111 * Without the final shift, the multiply proper is 19 instructions, 112 * 10 cycles and uses only 4 temporaries. Whew! 113 * 114 * You are not expected to understand this. 115 */ 116 static __always_inline u32 __attribute_const__ 117 hash_64(u64 a, unsigned int bits) 118 { 119 u64 b, c, d; 120 121 /* 122 * Encourage GCC to move a dynamic shift to %sar early, 123 * thereby freeing up an additional temporary register. 124 */ 125 if (!__builtin_constant_p(bits)) 126 asm("" : "=q" (bits) : "0" (64 - bits)); 127 else 128 bits = 64 - bits; 129 130 _ASSIGN(b, a*5); c = a << 13; 131 b = (b << 2) + a; _ASSIGN(d, a << 17); 132 a = b + (a << 1); c += d; 133 d = a << 10; _ASSIGN(a, a << 19); 134 d = a - d; _ASSIGN(a, a << 4, "X" (d)); 135 c += b; a += b; 136 d -= c; c += a << 1; 137 a += c << 3; _ASSIGN(b, b << (7+31), "X" (c), "X" (d)); 138 a <<= 31; b += d; 139 a += b; 140 return a >> bits; 141 } 142 #undef _ASSIGN /* We're a widely-used header file, so don't litter! */ 143 144 #endif /* BITS_PER_LONG == 64 */ 145 146 #endif /* _ASM_HASH_H */ 147