1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* asm/dma.h: Defines for using and allocating dma channels. 3 * Written by Hennus Bergman, 1992. 4 * High DMA channel support & info by Hannu Savolainen 5 * and John Boyd, Nov. 1992. 6 * (c) Copyright 2000, Grant Grundler 7 */ 8 9 #ifndef _ASM_DMA_H 10 #define _ASM_DMA_H 11 12 #include <asm/io.h> /* need byte IO */ 13 14 #define dma_outb outb 15 #define dma_inb inb 16 17 /* 18 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up 19 ** (or rather not merge) DMAs into manageable chunks. 20 ** On parisc, this is more of the software/tuning constraint 21 ** rather than the HW. I/O MMU allocation algorithms can be 22 ** faster with smaller sizes (to some degree). 23 */ 24 #define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE) 25 26 /* The maximum address that we can perform a DMA transfer to on this platform 27 ** New dynamic DMA interfaces should obsolete this.... 28 */ 29 #define MAX_DMA_ADDRESS (~0UL) 30 31 /* 32 ** We don't have DMA channels... well V-class does but the 33 ** Dynamic DMA Mapping interface will support them... right? :^) 34 ** Note: this is not relevant right now for PA-RISC, but we cannot 35 ** leave this as undefined because some things (e.g. sound) 36 ** won't compile :-( 37 */ 38 #define MAX_DMA_CHANNELS 8 39 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 40 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 41 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 42 43 #define DMA_AUTOINIT 0x10 44 45 /* 8237 DMA controllers */ 46 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 47 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 48 49 /* DMA controller registers */ 50 #define DMA1_CMD_REG 0x08 /* command register (w) */ 51 #define DMA1_STAT_REG 0x08 /* status register (r) */ 52 #define DMA1_REQ_REG 0x09 /* request register (w) */ 53 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 54 #define DMA1_MODE_REG 0x0B /* mode register (w) */ 55 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 56 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 57 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 58 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 59 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 60 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) 61 62 #define DMA2_CMD_REG 0xD0 /* command register (w) */ 63 #define DMA2_STAT_REG 0xD0 /* status register (r) */ 64 #define DMA2_REQ_REG 0xD2 /* request register (w) */ 65 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 66 #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 67 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 68 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 69 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 70 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 71 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 72 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) 73 74 static __inline__ unsigned long claim_dma_lock(void) 75 { 76 return 0; 77 } 78 79 static __inline__ void release_dma_lock(unsigned long flags) 80 { 81 } 82 83 84 /* Get DMA residue count. After a DMA transfer, this 85 * should return zero. Reading this while a DMA transfer is 86 * still in progress will return unpredictable results. 87 * If called before the channel has been used, it may return 1. 88 * Otherwise, it returns the number of _bytes_ left to transfer. 89 * 90 * Assumes DMA flip-flop is clear. 91 */ 92 static __inline__ int get_dma_residue(unsigned int dmanr) 93 { 94 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 95 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 96 97 /* using short to get 16-bit wrap around */ 98 unsigned short count; 99 100 count = 1 + dma_inb(io_port); 101 count += dma_inb(io_port) << 8; 102 103 return (dmanr<=3)? count : (count<<1); 104 } 105 106 /* enable/disable a specific DMA channel */ 107 static __inline__ void enable_dma(unsigned int dmanr) 108 { 109 #ifdef CONFIG_SUPERIO 110 if (dmanr<=3) 111 dma_outb(dmanr, DMA1_MASK_REG); 112 else 113 dma_outb(dmanr & 3, DMA2_MASK_REG); 114 #endif 115 } 116 117 static __inline__ void disable_dma(unsigned int dmanr) 118 { 119 #ifdef CONFIG_SUPERIO 120 if (dmanr<=3) 121 dma_outb(dmanr | 4, DMA1_MASK_REG); 122 else 123 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 124 #endif 125 } 126 127 /* reserve a DMA channel */ 128 #define request_dma(dmanr, device_id) (0) 129 130 /* Clear the 'DMA Pointer Flip Flop'. 131 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 132 * Use this once to initialize the FF to a known state. 133 * After that, keep track of it. :-) 134 * --- In order to do that, the DMA routines below should --- 135 * --- only be used while holding the DMA lock ! --- 136 */ 137 static __inline__ void clear_dma_ff(unsigned int dmanr) 138 { 139 } 140 141 /* set mode (above) for a specific DMA channel */ 142 static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 143 { 144 } 145 146 /* Set only the page register bits of the transfer address. 147 * This is used for successive transfers when we know the contents of 148 * the lower 16 bits of the DMA current address register, but a 64k boundary 149 * may have been crossed. 150 */ 151 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 152 { 153 } 154 155 156 /* Set transfer address & page bits for specific DMA channel. 157 * Assumes dma flipflop is clear. 158 */ 159 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 160 { 161 } 162 163 164 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 165 * a specific DMA channel. 166 * You must ensure the parameters are valid. 167 * NOTE: from a manual: "the number of transfers is one more 168 * than the initial word count"! This is taken into account. 169 * Assumes dma flip-flop is clear. 170 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 171 */ 172 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 173 { 174 } 175 176 177 #define free_dma(dmanr) 178 179 #ifdef CONFIG_PCI 180 extern int isa_dma_bridge_buggy; 181 #else 182 #define isa_dma_bridge_buggy (0) 183 #endif 184 185 #endif /* _ASM_DMA_H */ 186