1 #ifndef _PARISC_DMA_MAPPING_H 2 #define _PARISC_DMA_MAPPING_H 3 4 #include <linux/mm.h> 5 #include <asm/cacheflush.h> 6 #include <asm/scatterlist.h> 7 8 /* See Documentation/PCI/PCI-DMA-mapping.txt */ 9 struct hppa_dma_ops { 10 int (*dma_supported)(struct device *dev, u64 mask); 11 void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag); 12 void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag); 13 void (*free_consistent)(struct device *dev, size_t size, void *vaddr, dma_addr_t iova); 14 dma_addr_t (*map_single)(struct device *dev, void *addr, size_t size, enum dma_data_direction direction); 15 void (*unmap_single)(struct device *dev, dma_addr_t iova, size_t size, enum dma_data_direction direction); 16 int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction); 17 void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nhwents, enum dma_data_direction direction); 18 void (*dma_sync_single_for_cpu)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction); 19 void (*dma_sync_single_for_device)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction); 20 void (*dma_sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction); 21 void (*dma_sync_sg_for_device)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction); 22 }; 23 24 /* 25 ** We could live without the hppa_dma_ops indirection if we didn't want 26 ** to support 4 different coherent dma models with one binary (they will 27 ** someday be loadable modules): 28 ** I/O MMU consistent method dma_sync behavior 29 ** ============= ====================== ======================= 30 ** a) PA-7x00LC uncachable host memory flush/purge 31 ** b) U2/Uturn cachable host memory NOP 32 ** c) Ike/Astro cachable host memory NOP 33 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel 34 ** 35 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU. 36 ** 37 ** Systems (eg PCX-T workstations) that don't fall into the above 38 ** categories will need to modify the needed drivers to perform 39 ** flush/purge and allocate "regular" cacheable pages for everything. 40 */ 41 42 #ifdef CONFIG_PA11 43 extern struct hppa_dma_ops pcxl_dma_ops; 44 extern struct hppa_dma_ops pcx_dma_ops; 45 #endif 46 47 extern struct hppa_dma_ops *hppa_dma_ops; 48 49 static inline void * 50 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, 51 gfp_t flag) 52 { 53 return hppa_dma_ops->alloc_consistent(dev, size, dma_handle, flag); 54 } 55 56 static inline void * 57 dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, 58 gfp_t flag) 59 { 60 return hppa_dma_ops->alloc_noncoherent(dev, size, dma_handle, flag); 61 } 62 63 static inline void 64 dma_free_coherent(struct device *dev, size_t size, 65 void *vaddr, dma_addr_t dma_handle) 66 { 67 hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle); 68 } 69 70 static inline void 71 dma_free_noncoherent(struct device *dev, size_t size, 72 void *vaddr, dma_addr_t dma_handle) 73 { 74 hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle); 75 } 76 77 static inline dma_addr_t 78 dma_map_single(struct device *dev, void *ptr, size_t size, 79 enum dma_data_direction direction) 80 { 81 return hppa_dma_ops->map_single(dev, ptr, size, direction); 82 } 83 84 static inline void 85 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 86 enum dma_data_direction direction) 87 { 88 hppa_dma_ops->unmap_single(dev, dma_addr, size, direction); 89 } 90 91 static inline int 92 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 93 enum dma_data_direction direction) 94 { 95 return hppa_dma_ops->map_sg(dev, sg, nents, direction); 96 } 97 98 static inline void 99 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, 100 enum dma_data_direction direction) 101 { 102 hppa_dma_ops->unmap_sg(dev, sg, nhwentries, direction); 103 } 104 105 static inline dma_addr_t 106 dma_map_page(struct device *dev, struct page *page, unsigned long offset, 107 size_t size, enum dma_data_direction direction) 108 { 109 return dma_map_single(dev, (page_address(page) + (offset)), size, direction); 110 } 111 112 static inline void 113 dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, 114 enum dma_data_direction direction) 115 { 116 dma_unmap_single(dev, dma_address, size, direction); 117 } 118 119 120 static inline void 121 dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, 122 enum dma_data_direction direction) 123 { 124 if(hppa_dma_ops->dma_sync_single_for_cpu) 125 hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, 0, size, direction); 126 } 127 128 static inline void 129 dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, 130 enum dma_data_direction direction) 131 { 132 if(hppa_dma_ops->dma_sync_single_for_device) 133 hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, 0, size, direction); 134 } 135 136 static inline void 137 dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, 138 unsigned long offset, size_t size, 139 enum dma_data_direction direction) 140 { 141 if(hppa_dma_ops->dma_sync_single_for_cpu) 142 hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, offset, size, direction); 143 } 144 145 static inline void 146 dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, 147 unsigned long offset, size_t size, 148 enum dma_data_direction direction) 149 { 150 if(hppa_dma_ops->dma_sync_single_for_device) 151 hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, offset, size, direction); 152 } 153 154 static inline void 155 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, 156 enum dma_data_direction direction) 157 { 158 if(hppa_dma_ops->dma_sync_sg_for_cpu) 159 hppa_dma_ops->dma_sync_sg_for_cpu(dev, sg, nelems, direction); 160 } 161 162 static inline void 163 dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, 164 enum dma_data_direction direction) 165 { 166 if(hppa_dma_ops->dma_sync_sg_for_device) 167 hppa_dma_ops->dma_sync_sg_for_device(dev, sg, nelems, direction); 168 } 169 170 static inline int 171 dma_supported(struct device *dev, u64 mask) 172 { 173 return hppa_dma_ops->dma_supported(dev, mask); 174 } 175 176 static inline int 177 dma_set_mask(struct device *dev, u64 mask) 178 { 179 if(!dev->dma_mask || !dma_supported(dev, mask)) 180 return -EIO; 181 182 *dev->dma_mask = mask; 183 184 return 0; 185 } 186 187 static inline void 188 dma_cache_sync(struct device *dev, void *vaddr, size_t size, 189 enum dma_data_direction direction) 190 { 191 if(hppa_dma_ops->dma_sync_single_for_cpu) 192 flush_kernel_dcache_range((unsigned long)vaddr, size); 193 } 194 195 static inline void * 196 parisc_walk_tree(struct device *dev) 197 { 198 struct device *otherdev; 199 if(likely(dev->platform_data != NULL)) 200 return dev->platform_data; 201 /* OK, just traverse the bus to find it */ 202 for(otherdev = dev->parent; otherdev; 203 otherdev = otherdev->parent) { 204 if(otherdev->platform_data) { 205 dev->platform_data = otherdev->platform_data; 206 break; 207 } 208 } 209 BUG_ON(!dev->platform_data); 210 return dev->platform_data; 211 } 212 213 #define GET_IOC(dev) (HBA_DATA(parisc_walk_tree(dev))->iommu); 214 215 216 #ifdef CONFIG_IOMMU_CCIO 217 struct parisc_device; 218 struct ioc; 219 void * ccio_get_iommu(const struct parisc_device *dev); 220 int ccio_request_resource(const struct parisc_device *dev, 221 struct resource *res); 222 int ccio_allocate_resource(const struct parisc_device *dev, 223 struct resource *res, unsigned long size, 224 unsigned long min, unsigned long max, unsigned long align); 225 #else /* !CONFIG_IOMMU_CCIO */ 226 #define ccio_get_iommu(dev) NULL 227 #define ccio_request_resource(dev, res) insert_resource(&iomem_resource, res) 228 #define ccio_allocate_resource(dev, res, size, min, max, align) \ 229 allocate_resource(&iomem_resource, res, size, min, max, \ 230 align, NULL, NULL) 231 #endif /* !CONFIG_IOMMU_CCIO */ 232 233 #ifdef CONFIG_IOMMU_SBA 234 struct parisc_device; 235 void * sba_get_iommu(struct parisc_device *dev); 236 #endif 237 238 /* At the moment, we panic on error for IOMMU resource exaustion */ 239 #define dma_mapping_error(dev, x) 0 240 241 #endif 242