1 #ifndef _PARISC_DMA_MAPPING_H 2 #define _PARISC_DMA_MAPPING_H 3 4 #include <linux/mm.h> 5 #include <linux/scatterlist.h> 6 #include <asm/cacheflush.h> 7 8 /* See Documentation/DMA-API-HOWTO.txt */ 9 struct hppa_dma_ops { 10 int (*dma_supported)(struct device *dev, u64 mask); 11 void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag); 12 void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag); 13 void (*free_consistent)(struct device *dev, size_t size, void *vaddr, dma_addr_t iova); 14 dma_addr_t (*map_single)(struct device *dev, void *addr, size_t size, enum dma_data_direction direction); 15 void (*unmap_single)(struct device *dev, dma_addr_t iova, size_t size, enum dma_data_direction direction); 16 int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction); 17 void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nhwents, enum dma_data_direction direction); 18 void (*dma_sync_single_for_cpu)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction); 19 void (*dma_sync_single_for_device)(struct device *dev, dma_addr_t iova, unsigned long offset, size_t size, enum dma_data_direction direction); 20 void (*dma_sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction); 21 void (*dma_sync_sg_for_device)(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction); 22 }; 23 24 /* 25 ** We could live without the hppa_dma_ops indirection if we didn't want 26 ** to support 4 different coherent dma models with one binary (they will 27 ** someday be loadable modules): 28 ** I/O MMU consistent method dma_sync behavior 29 ** ============= ====================== ======================= 30 ** a) PA-7x00LC uncachable host memory flush/purge 31 ** b) U2/Uturn cachable host memory NOP 32 ** c) Ike/Astro cachable host memory NOP 33 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel 34 ** 35 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU. 36 ** 37 ** Systems (eg PCX-T workstations) that don't fall into the above 38 ** categories will need to modify the needed drivers to perform 39 ** flush/purge and allocate "regular" cacheable pages for everything. 40 */ 41 42 #ifdef CONFIG_PA11 43 extern struct hppa_dma_ops pcxl_dma_ops; 44 extern struct hppa_dma_ops pcx_dma_ops; 45 #endif 46 47 extern struct hppa_dma_ops *hppa_dma_ops; 48 49 #define dma_alloc_attrs(d, s, h, f, a) dma_alloc_coherent(d, s, h, f) 50 #define dma_free_attrs(d, s, h, f, a) dma_free_coherent(d, s, h, f) 51 52 static inline void * 53 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, 54 gfp_t flag) 55 { 56 return hppa_dma_ops->alloc_consistent(dev, size, dma_handle, flag); 57 } 58 59 static inline void * 60 dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, 61 gfp_t flag) 62 { 63 return hppa_dma_ops->alloc_noncoherent(dev, size, dma_handle, flag); 64 } 65 66 static inline void 67 dma_free_coherent(struct device *dev, size_t size, 68 void *vaddr, dma_addr_t dma_handle) 69 { 70 hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle); 71 } 72 73 static inline void 74 dma_free_noncoherent(struct device *dev, size_t size, 75 void *vaddr, dma_addr_t dma_handle) 76 { 77 hppa_dma_ops->free_consistent(dev, size, vaddr, dma_handle); 78 } 79 80 static inline dma_addr_t 81 dma_map_single(struct device *dev, void *ptr, size_t size, 82 enum dma_data_direction direction) 83 { 84 return hppa_dma_ops->map_single(dev, ptr, size, direction); 85 } 86 87 static inline void 88 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 89 enum dma_data_direction direction) 90 { 91 hppa_dma_ops->unmap_single(dev, dma_addr, size, direction); 92 } 93 94 static inline int 95 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 96 enum dma_data_direction direction) 97 { 98 return hppa_dma_ops->map_sg(dev, sg, nents, direction); 99 } 100 101 static inline void 102 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, 103 enum dma_data_direction direction) 104 { 105 hppa_dma_ops->unmap_sg(dev, sg, nhwentries, direction); 106 } 107 108 static inline dma_addr_t 109 dma_map_page(struct device *dev, struct page *page, unsigned long offset, 110 size_t size, enum dma_data_direction direction) 111 { 112 return dma_map_single(dev, (page_address(page) + (offset)), size, direction); 113 } 114 115 static inline void 116 dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, 117 enum dma_data_direction direction) 118 { 119 dma_unmap_single(dev, dma_address, size, direction); 120 } 121 122 123 static inline void 124 dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, 125 enum dma_data_direction direction) 126 { 127 if(hppa_dma_ops->dma_sync_single_for_cpu) 128 hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, 0, size, direction); 129 } 130 131 static inline void 132 dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, 133 enum dma_data_direction direction) 134 { 135 if(hppa_dma_ops->dma_sync_single_for_device) 136 hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, 0, size, direction); 137 } 138 139 static inline void 140 dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, 141 unsigned long offset, size_t size, 142 enum dma_data_direction direction) 143 { 144 if(hppa_dma_ops->dma_sync_single_for_cpu) 145 hppa_dma_ops->dma_sync_single_for_cpu(dev, dma_handle, offset, size, direction); 146 } 147 148 static inline void 149 dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, 150 unsigned long offset, size_t size, 151 enum dma_data_direction direction) 152 { 153 if(hppa_dma_ops->dma_sync_single_for_device) 154 hppa_dma_ops->dma_sync_single_for_device(dev, dma_handle, offset, size, direction); 155 } 156 157 static inline void 158 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, 159 enum dma_data_direction direction) 160 { 161 if(hppa_dma_ops->dma_sync_sg_for_cpu) 162 hppa_dma_ops->dma_sync_sg_for_cpu(dev, sg, nelems, direction); 163 } 164 165 static inline void 166 dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, 167 enum dma_data_direction direction) 168 { 169 if(hppa_dma_ops->dma_sync_sg_for_device) 170 hppa_dma_ops->dma_sync_sg_for_device(dev, sg, nelems, direction); 171 } 172 173 static inline int 174 dma_supported(struct device *dev, u64 mask) 175 { 176 return hppa_dma_ops->dma_supported(dev, mask); 177 } 178 179 static inline int 180 dma_set_mask(struct device *dev, u64 mask) 181 { 182 if(!dev->dma_mask || !dma_supported(dev, mask)) 183 return -EIO; 184 185 *dev->dma_mask = mask; 186 187 return 0; 188 } 189 190 static inline void 191 dma_cache_sync(struct device *dev, void *vaddr, size_t size, 192 enum dma_data_direction direction) 193 { 194 if(hppa_dma_ops->dma_sync_single_for_cpu) 195 flush_kernel_dcache_range((unsigned long)vaddr, size); 196 } 197 198 static inline void * 199 parisc_walk_tree(struct device *dev) 200 { 201 struct device *otherdev; 202 if(likely(dev->platform_data != NULL)) 203 return dev->platform_data; 204 /* OK, just traverse the bus to find it */ 205 for(otherdev = dev->parent; otherdev; 206 otherdev = otherdev->parent) { 207 if(otherdev->platform_data) { 208 dev->platform_data = otherdev->platform_data; 209 break; 210 } 211 } 212 BUG_ON(!dev->platform_data); 213 return dev->platform_data; 214 } 215 216 #define GET_IOC(dev) (HBA_DATA(parisc_walk_tree(dev))->iommu) 217 218 219 #ifdef CONFIG_IOMMU_CCIO 220 struct parisc_device; 221 struct ioc; 222 void * ccio_get_iommu(const struct parisc_device *dev); 223 int ccio_request_resource(const struct parisc_device *dev, 224 struct resource *res); 225 int ccio_allocate_resource(const struct parisc_device *dev, 226 struct resource *res, unsigned long size, 227 unsigned long min, unsigned long max, unsigned long align); 228 #else /* !CONFIG_IOMMU_CCIO */ 229 #define ccio_get_iommu(dev) NULL 230 #define ccio_request_resource(dev, res) insert_resource(&iomem_resource, res) 231 #define ccio_allocate_resource(dev, res, size, min, max, align) \ 232 allocate_resource(&iomem_resource, res, size, min, max, \ 233 align, NULL, NULL) 234 #endif /* !CONFIG_IOMMU_CCIO */ 235 236 #ifdef CONFIG_IOMMU_SBA 237 struct parisc_device; 238 void * sba_get_iommu(struct parisc_device *dev); 239 #endif 240 241 /* At the moment, we panic on error for IOMMU resource exaustion */ 242 #define dma_mapping_error(dev, x) 0 243 244 /* This API cannot be supported on PA-RISC */ 245 static inline int dma_mmap_coherent(struct device *dev, 246 struct vm_area_struct *vma, void *cpu_addr, 247 dma_addr_t dma_addr, size_t size) 248 { 249 return -EINVAL; 250 } 251 252 static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt, 253 void *cpu_addr, dma_addr_t dma_addr, 254 size_t size) 255 { 256 return -EINVAL; 257 } 258 259 #endif 260