1 /* 2 * OpenRISC irq.c 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/of.h> 20 #include <linux/ftrace.h> 21 #include <linux/irq.h> 22 #include <linux/export.h> 23 #include <linux/irqdomain.h> 24 #include <linux/irqflags.h> 25 26 /* read interrupt enabled status */ 27 unsigned long arch_local_save_flags(void) 28 { 29 return mfspr(SPR_SR) & (SPR_SR_IEE|SPR_SR_TEE); 30 } 31 EXPORT_SYMBOL(arch_local_save_flags); 32 33 /* set interrupt enabled status */ 34 void arch_local_irq_restore(unsigned long flags) 35 { 36 mtspr(SPR_SR, ((mfspr(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE)) | flags)); 37 } 38 EXPORT_SYMBOL(arch_local_irq_restore); 39 40 41 /* OR1K PIC implementation */ 42 43 /* We're a couple of cycles faster than the generic implementations with 44 * these 'fast' versions. 45 */ 46 47 static void or1k_pic_mask(struct irq_data *data) 48 { 49 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->irq)); 50 } 51 52 static void or1k_pic_unmask(struct irq_data *data) 53 { 54 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->irq)); 55 } 56 57 static void or1k_pic_ack(struct irq_data *data) 58 { 59 /* EDGE-triggered interrupts need to be ack'ed in order to clear 60 * the latch. 61 * LEVER-triggered interrupts do not need to be ack'ed; however, 62 * ack'ing the interrupt has no ill-effect and is quicker than 63 * trying to figure out what type it is... 64 */ 65 66 /* The OpenRISC 1000 spec says to write a 1 to the bit to ack the 67 * interrupt, but the OR1200 does this backwards and requires a 0 68 * to be written... 69 */ 70 71 #ifdef CONFIG_OR1K_1200 72 /* There are two oddities with the OR1200 PIC implementation: 73 * i) LEVEL-triggered interrupts are latched and need to be cleared 74 * ii) the interrupt latch is cleared by writing a 0 to the bit, 75 * as opposed to a 1 as mandated by the spec 76 */ 77 78 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq)); 79 #else 80 WARN(1, "Interrupt handling possibily broken\n"); 81 mtspr(SPR_PICSR, (1UL << irq)); 82 #endif 83 } 84 85 static void or1k_pic_mask_ack(struct irq_data *data) 86 { 87 /* Comments for pic_ack apply here, too */ 88 89 #ifdef CONFIG_OR1K_1200 90 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq)); 91 #else 92 WARN(1, "Interrupt handling possibily broken\n"); 93 mtspr(SPR_PICSR, (1UL << irq)); 94 #endif 95 } 96 97 #if 0 98 static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type) 99 { 100 /* There's nothing to do in the PIC configuration when changing 101 * flow type. Level and edge-triggered interrupts are both 102 * supported, but it's PIC-implementation specific which type 103 * is handled. */ 104 105 return irq_setup_alt_chip(data, flow_type); 106 } 107 #endif 108 109 static struct irq_chip or1k_dev = { 110 .name = "or1k-PIC", 111 .irq_unmask = or1k_pic_unmask, 112 .irq_mask = or1k_pic_mask, 113 .irq_ack = or1k_pic_ack, 114 .irq_mask_ack = or1k_pic_mask_ack, 115 }; 116 117 static struct irq_domain *root_domain; 118 119 static inline int pic_get_irq(int first) 120 { 121 int hwirq; 122 123 hwirq = ffs(mfspr(SPR_PICSR) >> first); 124 if (!hwirq) 125 return NO_IRQ; 126 else 127 hwirq = hwirq + first -1; 128 129 return irq_find_mapping(root_domain, hwirq); 130 } 131 132 133 static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 134 { 135 irq_set_chip_and_handler_name(irq, &or1k_dev, 136 handle_level_irq, "level"); 137 irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE); 138 139 return 0; 140 } 141 142 static const struct irq_domain_ops or1k_irq_domain_ops = { 143 .xlate = irq_domain_xlate_onecell, 144 .map = or1k_map, 145 }; 146 147 /* 148 * This sets up the IRQ domain for the PIC built in to the OpenRISC 149 * 1000 CPU. This is the "root" domain as these are the interrupts 150 * that directly trigger an exception in the CPU. 151 */ 152 static void __init or1k_irq_init(void) 153 { 154 struct device_node *intc = NULL; 155 156 /* The interrupt controller device node is mandatory */ 157 intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic"); 158 BUG_ON(!intc); 159 160 /* Disable all interrupts until explicitly requested */ 161 mtspr(SPR_PICMR, (0UL)); 162 163 root_domain = irq_domain_add_linear(intc, 32, 164 &or1k_irq_domain_ops, NULL); 165 } 166 167 void __init init_IRQ(void) 168 { 169 or1k_irq_init(); 170 } 171 172 void __irq_entry do_IRQ(struct pt_regs *regs) 173 { 174 int irq = -1; 175 struct pt_regs *old_regs = set_irq_regs(regs); 176 177 irq_enter(); 178 179 while ((irq = pic_get_irq(irq + 1)) != NO_IRQ) 180 generic_handle_irq(irq); 181 182 irq_exit(); 183 set_irq_regs(old_regs); 184 } 185