1/* 2 * Copyright (C) 2015 Altera Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17/dts-v1/; 18 19/ { 20 model = "Altera NiosII Max10"; 21 compatible = "altr,niosii-max10"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu: cpu@0 { 30 device_type = "cpu"; 31 compatible = "altr,nios2-1.1"; 32 reg = <0x00000000>; 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 altr,exception-addr = <0xc8000120>; 36 altr,fast-tlb-miss-addr = <0xc0000100>; 37 altr,has-div = <1>; 38 altr,has-initda = <1>; 39 altr,has-mmu = <1>; 40 altr,has-mul = <1>; 41 altr,implementation = "fast"; 42 altr,pid-num-bits = <8>; 43 altr,reset-addr = <0xd4000000>; 44 altr,tlb-num-entries = <256>; 45 altr,tlb-num-ways = <16>; 46 altr,tlb-ptr-sz = <8>; 47 clock-frequency = <75000000>; 48 dcache-line-size = <32>; 49 dcache-size = <32768>; 50 icache-line-size = <32>; 51 icache-size = <32768>; 52 }; 53 }; 54 55 memory { 56 device_type = "memory"; 57 reg = <0x08000000 0x08000000>, 58 <0x00000000 0x00000400>; 59 }; 60 61 sopc0: sopc@0 { 62 device_type = "soc"; 63 ranges; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "altr,avalon", "simple-bus"; 67 bus-frequency = <75000000>; 68 69 jtag_uart: serial@18001530 { 70 compatible = "altr,juart-1.0"; 71 reg = <0x18001530 0x00000008>; 72 interrupt-parent = <&cpu>; 73 interrupts = <7>; 74 }; 75 76 a_16550_uart_0: serial@18001600 { 77 compatible = "altr,16550-FIFO32", "ns16550a"; 78 reg = <0x18001600 0x00000200>; 79 interrupt-parent = <&cpu>; 80 interrupts = <1>; 81 auto-flow-control = <1>; 82 clock-frequency = <50000000>; 83 fifo-size = <32>; 84 reg-io-width = <4>; 85 reg-shift = <2>; 86 }; 87 88 sysid: sysid@18001528 { 89 compatible = "altr,sysid-1.0"; 90 reg = <0x18001528 0x00000008>; 91 id = <4207856382>; 92 timestamp = <1431309290>; 93 }; 94 95 rgmii_0_eth_tse_0: ethernet@400 { 96 compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0"; 97 reg = <0x00000400 0x00000400>, 98 <0x00000820 0x00000020>, 99 <0x00000800 0x00000020>, 100 <0x000008c0 0x00000008>, 101 <0x00000840 0x00000020>, 102 <0x00000860 0x00000020>; 103 reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; 104 interrupt-parent = <&cpu>; 105 interrupts = <2 3>; 106 interrupt-names = "rx_irq", "tx_irq"; 107 rx-fifo-depth = <8192>; 108 tx-fifo-depth = <8192>; 109 address-bits = <48>; 110 max-frame-size = <1518>; 111 local-mac-address = [00 00 00 00 00 00]; 112 altr,has-supplementary-unicast; 113 altr,enable-sup-addr = <1>; 114 altr,has-hash-multicast-filter; 115 altr,enable-hash = <1>; 116 phy-mode = "rgmii-id"; 117 phy-handle = <&phy0>; 118 rgmii_0_eth_tse_0_mdio: mdio { 119 compatible = "altr,tse-mdio"; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 phy0: ethernet-phy@0 { 123 reg = <0>; 124 device_type = "ethernet-phy"; 125 }; 126 }; 127 }; 128 129 enet_pll: clock@0 { 130 compatible = "altr,pll-1.0"; 131 #clock-cells = <1>; 132 133 enet_pll_c0: enet_pll_c0 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <125000000>; 137 clock-output-names = "enet_pll-c0"; 138 }; 139 140 enet_pll_c1: enet_pll_c1 { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <25000000>; 144 clock-output-names = "enet_pll-c1"; 145 }; 146 147 enet_pll_c2: enet_pll_c2 { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <2500000>; 151 clock-output-names = "enet_pll-c2"; 152 }; 153 }; 154 155 sys_pll: clock@1 { 156 compatible = "altr,pll-1.0"; 157 #clock-cells = <1>; 158 159 sys_pll_c0: sys_pll_c0 { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency = <100000000>; 163 clock-output-names = "sys_pll-c0"; 164 }; 165 166 sys_pll_c1: sys_pll_c1 { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 clock-frequency = <50000000>; 170 clock-output-names = "sys_pll-c1"; 171 }; 172 173 sys_pll_c2: sys_pll_c2 { 174 compatible = "fixed-clock"; 175 #clock-cells = <0>; 176 clock-frequency = <75000000>; 177 clock-output-names = "sys_pll-c2"; 178 }; 179 }; 180 181 sys_clk_timer: timer@18001440 { 182 compatible = "altr,timer-1.0"; 183 reg = <0x18001440 0x00000020>; 184 interrupt-parent = <&cpu>; 185 interrupts = <0>; 186 clock-frequency = <75000000>; 187 }; 188 189 led_pio: gpio@180014d0 { 190 compatible = "altr,pio-1.0"; 191 reg = <0x180014d0 0x00000010>; 192 altr,gpio-bank-width = <4>; 193 resetvalue = <15>; 194 #gpio-cells = <2>; 195 gpio-controller; 196 }; 197 198 button_pio: gpio@180014c0 { 199 compatible = "altr,pio-1.0"; 200 reg = <0x180014c0 0x00000010>; 201 interrupt-parent = <&cpu>; 202 interrupts = <6>; 203 altr,gpio-bank-width = <3>; 204 altr,interrupt-type = <2>; 205 edge_type = <1>; 206 level_trigger = <0>; 207 resetvalue = <0>; 208 #gpio-cells = <2>; 209 gpio-controller; 210 }; 211 212 sys_clk_timer_1: timer@880 { 213 compatible = "altr,timer-1.0"; 214 reg = <0x00000880 0x00000020>; 215 interrupt-parent = <&cpu>; 216 interrupts = <5>; 217 clock-frequency = <75000000>; 218 }; 219 220 fpga_leds: leds { 221 compatible = "gpio-leds"; 222 223 led_fpga0: fpga0 { 224 label = "fpga_led0"; 225 gpios = <&led_pio 0 1>; 226 }; 227 228 led_fpga1: fpga1 { 229 label = "fpga_led1"; 230 gpios = <&led_pio 1 1>; 231 }; 232 233 led_fpga2: fpga2 { 234 label = "fpga_led2"; 235 gpios = <&led_pio 2 1>; 236 }; 237 238 led_fpga3: fpga3 { 239 label = "fpga_led3"; 240 gpios = <&led_pio 3 1>; 241 }; 242 }; 243 }; 244 245 chosen { 246 bootargs = "debug console=ttyS0,115200"; 247 }; 248}; 249