1 /* 2 * Toshiba rbtx4927 specific setup 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright 2001-2002 MontaVista Software Inc. 8 * 9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) 10 * Copyright (C) 2000 RidgeRun, Inc. 11 * Author: RidgeRun, Inc. 12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com 13 * 14 * Copyright 2001 MontaVista Software Inc. 15 * Author: jsun@mvista.com or jsun@junsun.net 16 * 17 * Copyright 2002 MontaVista Software Inc. 18 * Author: Michael Pruznick, michael_pruznick@mvista.com 19 * 20 * Copyright (C) 2000-2001 Toshiba Corporation 21 * 22 * Copyright (C) 2004 MontaVista Software Inc. 23 * Author: Manish Lachwani, mlachwani@mvista.com 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms of the GNU General Public License as published by the 27 * Free Software Foundation; either version 2 of the License, or (at your 28 * option) any later version. 29 * 30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * You should have received a copy of the GNU General Public License along 42 * with this program; if not, write to the Free Software Foundation, Inc., 43 * 675 Mass Ave, Cambridge, MA 02139, USA. 44 */ 45 #include <linux/init.h> 46 #include <linux/kernel.h> 47 #include <linux/types.h> 48 #include <linux/ioport.h> 49 #include <linux/platform_device.h> 50 #include <linux/delay.h> 51 #include <asm/io.h> 52 #include <asm/reboot.h> 53 #include <asm/txx9/generic.h> 54 #include <asm/txx9/pci.h> 55 #include <asm/txx9/rbtx4927.h> 56 #include <asm/txx9/tx4938.h> /* for TX4937 */ 57 58 #ifdef CONFIG_PCI 59 static void __init tx4927_pci_setup(void) 60 { 61 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); 62 struct pci_controller *c = &txx9_primary_pcic; 63 64 register_pci_controller(c); 65 66 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) 67 txx9_pci_option = 68 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | 69 TXX9_PCI_OPT_CLK_66; /* already configured */ 70 71 /* Reset PCI Bus */ 72 writeb(1, rbtx4927_pcireset_addr); 73 /* Reset PCIC */ 74 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 75 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 76 TXX9_PCI_OPT_CLK_66) 77 tx4927_pciclk66_setup(); 78 mdelay(10); 79 /* clear PCIC reset */ 80 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 81 writeb(0, rbtx4927_pcireset_addr); 82 iob(); 83 84 tx4927_report_pciclk(); 85 tx4927_pcic_setup(tx4927_pcicptr, c, extarb); 86 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 87 TXX9_PCI_OPT_CLK_AUTO && 88 txx9_pci66_check(c, 0, 0)) { 89 /* Reset PCI Bus */ 90 writeb(1, rbtx4927_pcireset_addr); 91 /* Reset PCIC */ 92 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 93 tx4927_pciclk66_setup(); 94 mdelay(10); 95 /* clear PCIC reset */ 96 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); 97 writeb(0, rbtx4927_pcireset_addr); 98 iob(); 99 /* Reinitialize PCIC */ 100 tx4927_report_pciclk(); 101 tx4927_pcic_setup(tx4927_pcicptr, c, extarb); 102 } 103 tx4927_setup_pcierr_irq(); 104 } 105 106 static void __init tx4937_pci_setup(void) 107 { 108 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); 109 struct pci_controller *c = &txx9_primary_pcic; 110 111 register_pci_controller(c); 112 113 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) 114 txx9_pci_option = 115 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | 116 TXX9_PCI_OPT_CLK_66; /* already configured */ 117 118 /* Reset PCI Bus */ 119 writeb(1, rbtx4927_pcireset_addr); 120 /* Reset PCIC */ 121 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 122 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 123 TXX9_PCI_OPT_CLK_66) 124 tx4938_pciclk66_setup(); 125 mdelay(10); 126 /* clear PCIC reset */ 127 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 128 writeb(0, rbtx4927_pcireset_addr); 129 iob(); 130 131 tx4938_report_pciclk(); 132 tx4927_pcic_setup(tx4938_pcicptr, c, extarb); 133 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == 134 TXX9_PCI_OPT_CLK_AUTO && 135 txx9_pci66_check(c, 0, 0)) { 136 /* Reset PCI Bus */ 137 writeb(1, rbtx4927_pcireset_addr); 138 /* Reset PCIC */ 139 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 140 tx4938_pciclk66_setup(); 141 mdelay(10); 142 /* clear PCIC reset */ 143 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); 144 writeb(0, rbtx4927_pcireset_addr); 145 iob(); 146 /* Reinitialize PCIC */ 147 tx4938_report_pciclk(); 148 tx4927_pcic_setup(tx4938_pcicptr, c, extarb); 149 } 150 tx4938_setup_pcierr_irq(); 151 } 152 153 static void __init rbtx4927_arch_init(void) 154 { 155 tx4927_pci_setup(); 156 } 157 158 static void __init rbtx4937_arch_init(void) 159 { 160 tx4937_pci_setup(); 161 } 162 #else 163 #define rbtx4927_arch_init NULL 164 #define rbtx4937_arch_init NULL 165 #endif /* CONFIG_PCI */ 166 167 static void toshiba_rbtx4927_restart(char *command) 168 { 169 /* enable the s/w reset register */ 170 writeb(1, rbtx4927_softresetlock_addr); 171 172 /* wait for enable to be seen */ 173 while (!(readb(rbtx4927_softresetlock_addr) & 1)) 174 ; 175 176 /* do a s/w reset */ 177 writeb(1, rbtx4927_softreset_addr); 178 179 /* fallback */ 180 (*_machine_halt)(); 181 } 182 183 static void __init rbtx4927_clock_init(void); 184 static void __init rbtx4937_clock_init(void); 185 186 static void __init rbtx4927_mem_setup(void) 187 { 188 u32 cp0_config; 189 char *argptr; 190 191 /* enable caches -- HCP5 does this, pmon does not */ 192 cp0_config = read_c0_config(); 193 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 194 write_c0_config(cp0_config); 195 196 if (TX4927_REV_PCODE() == 0x4927) { 197 rbtx4927_clock_init(); 198 tx4927_setup(); 199 } else { 200 rbtx4937_clock_init(); 201 tx4938_setup(); 202 } 203 204 _machine_restart = toshiba_rbtx4927_restart; 205 206 #ifdef CONFIG_PCI 207 txx9_alloc_pci_controller(&txx9_primary_pcic, 208 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 209 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); 210 txx9_board_pcibios_setup = tx4927_pcibios_setup; 211 #else 212 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 213 #endif 214 215 tx4927_sio_init(0, 0); 216 #ifdef CONFIG_SERIAL_TXX9_CONSOLE 217 argptr = prom_getcmdline(); 218 if (!strstr(argptr, "console=")) 219 strcat(argptr, " console=ttyS0,38400"); 220 #endif 221 } 222 223 static void __init rbtx4927_clock_init(void) 224 { 225 /* 226 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 227 * 228 * For TX4927: 229 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). 230 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) 231 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) 232 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) 233 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) 234 * i.e. S9[3]: ON (83MHz), OFF (100MHz) 235 */ 236 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & 237 TX4927_CCFG_PCIDIVMODE_MASK) { 238 case TX4927_CCFG_PCIDIVMODE_2_5: 239 case TX4927_CCFG_PCIDIVMODE_5: 240 txx9_cpu_clock = 166666666; /* 166MHz */ 241 break; 242 default: 243 txx9_cpu_clock = 200000000; /* 200MHz */ 244 } 245 } 246 247 static void __init rbtx4937_clock_init(void) 248 { 249 /* 250 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 251 * 252 * For TX4937: 253 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) 254 * PCIDIVMODE[10] is 0. 255 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) 256 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) 257 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) 258 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) 259 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) 260 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) 261 */ 262 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & 263 TX4938_CCFG_PCIDIVMODE_MASK) { 264 case TX4938_CCFG_PCIDIVMODE_8: 265 case TX4938_CCFG_PCIDIVMODE_4: 266 txx9_cpu_clock = 266666666; /* 266MHz */ 267 break; 268 case TX4938_CCFG_PCIDIVMODE_9: 269 case TX4938_CCFG_PCIDIVMODE_4_5: 270 txx9_cpu_clock = 300000000; /* 300MHz */ 271 break; 272 default: 273 txx9_cpu_clock = 333333333; /* 333MHz */ 274 } 275 } 276 277 static void __init rbtx4927_time_init(void) 278 { 279 tx4927_time_init(0); 280 } 281 282 static void __init toshiba_rbtx4927_rtc_init(void) 283 { 284 struct resource res = { 285 .start = RBTX4927_BRAMRTC_BASE - IO_BASE, 286 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, 287 .flags = IORESOURCE_MEM, 288 }; 289 platform_device_register_simple("rtc-ds1742", -1, &res, 1); 290 } 291 292 static void __init rbtx4927_ne_init(void) 293 { 294 struct resource res[] = { 295 { 296 .start = RBTX4927_RTL_8019_BASE, 297 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, 298 .flags = IORESOURCE_IO, 299 }, { 300 .start = RBTX4927_RTL_8019_IRQ, 301 .flags = IORESOURCE_IRQ, 302 } 303 }; 304 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); 305 } 306 307 static void __init rbtx4927_device_init(void) 308 { 309 toshiba_rbtx4927_rtc_init(); 310 rbtx4927_ne_init(); 311 tx4927_wdt_init(); 312 } 313 314 struct txx9_board_vec rbtx4927_vec __initdata = { 315 .system = "Toshiba RBTX4927", 316 .prom_init = rbtx4927_prom_init, 317 .mem_setup = rbtx4927_mem_setup, 318 .irq_setup = rbtx4927_irq_setup, 319 .time_init = rbtx4927_time_init, 320 .device_init = rbtx4927_device_init, 321 .arch_init = rbtx4927_arch_init, 322 #ifdef CONFIG_PCI 323 .pci_map_irq = rbtx4927_pci_map_irq, 324 #endif 325 }; 326 struct txx9_board_vec rbtx4937_vec __initdata = { 327 .system = "Toshiba RBTX4937", 328 .prom_init = rbtx4927_prom_init, 329 .mem_setup = rbtx4927_mem_setup, 330 .irq_setup = rbtx4927_irq_setup, 331 .time_init = rbtx4927_time_init, 332 .device_init = rbtx4927_device_init, 333 .arch_init = rbtx4937_arch_init, 334 #ifdef CONFIG_PCI 335 .pci_map_irq = rbtx4927_pci_map_irq, 336 #endif 337 }; 338