1 /* 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 3 * and RBTX49xx patch from CELF patch archive. 4 * 5 * 2003-2005 (c) MontaVista Software, Inc. 6 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/interrupt.h> 16 #include <linux/string.h> 17 #include <linux/export.h> 18 #include <linux/clk-provider.h> 19 #include <linux/clkdev.h> 20 #include <linux/err.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/platform_device.h> 23 #include <linux/platform_data/txx9/ndfmc.h> 24 #include <linux/serial_core.h> 25 #include <linux/mtd/physmap.h> 26 #include <linux/leds.h> 27 #include <linux/device.h> 28 #include <linux/slab.h> 29 #include <linux/io.h> 30 #include <linux/irq.h> 31 #include <asm/bootinfo.h> 32 #include <asm/idle.h> 33 #include <asm/time.h> 34 #include <asm/reboot.h> 35 #include <asm/r4kcache.h> 36 #include <asm/setup.h> 37 #include <asm/txx9/generic.h> 38 #include <asm/txx9/pci.h> 39 #include <asm/txx9tmr.h> 40 #include <asm/txx9/dmac.h> 41 #ifdef CONFIG_CPU_TX49XX 42 #include <asm/txx9/tx4938.h> 43 #endif 44 45 /* EBUSC settings of TX4927, etc. */ 46 struct resource txx9_ce_res[8]; 47 static char txx9_ce_res_name[8][4]; /* "CEn" */ 48 49 /* pcode, internal register */ 50 unsigned int txx9_pcode; 51 char txx9_pcode_str[8]; 52 static struct resource txx9_reg_res = { 53 .name = txx9_pcode_str, 54 .flags = IORESOURCE_MEM, 55 }; 56 void __init 57 txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) 58 { 59 int i; 60 61 for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) { 62 sprintf(txx9_ce_res_name[i], "CE%d", i); 63 txx9_ce_res[i].flags = IORESOURCE_MEM; 64 txx9_ce_res[i].name = txx9_ce_res_name[i]; 65 } 66 67 txx9_pcode = pcode; 68 sprintf(txx9_pcode_str, "TX%x", pcode); 69 if (base) { 70 txx9_reg_res.start = base & 0xfffffffffULL; 71 txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1); 72 request_resource(&iomem_resource, &txx9_reg_res); 73 } 74 } 75 76 /* clocks */ 77 unsigned int txx9_master_clock; 78 unsigned int txx9_cpu_clock; 79 unsigned int txx9_gbus_clock; 80 81 #ifdef CONFIG_CPU_TX39XX 82 /* don't enable by default - see errata */ 83 int txx9_ccfg_toeon __initdata; 84 #else 85 int txx9_ccfg_toeon __initdata = 1; 86 #endif 87 88 #define BOARD_VEC(board) extern struct txx9_board_vec board; 89 #include <asm/txx9/boards.h> 90 #undef BOARD_VEC 91 92 struct txx9_board_vec *txx9_board_vec __initdata; 93 static char txx9_system_type[32]; 94 95 static struct txx9_board_vec *board_vecs[] __initdata = { 96 #define BOARD_VEC(board) &board, 97 #include <asm/txx9/boards.h> 98 #undef BOARD_VEC 99 }; 100 101 static struct txx9_board_vec *__init find_board_byname(const char *name) 102 { 103 int i; 104 105 /* search board_vecs table */ 106 for (i = 0; i < ARRAY_SIZE(board_vecs); i++) { 107 if (strstr(board_vecs[i]->system, name)) 108 return board_vecs[i]; 109 } 110 return NULL; 111 } 112 113 static void __init prom_init_cmdline(void) 114 { 115 int argc; 116 int *argv32; 117 int i; /* Always ignore the "-c" at argv[0] */ 118 119 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { 120 /* 121 * argc is not a valid number, or argv32 is not a valid 122 * pointer 123 */ 124 argc = 0; 125 argv32 = NULL; 126 } else { 127 argc = (int)fw_arg0; 128 argv32 = (int *)fw_arg1; 129 } 130 131 arcs_cmdline[0] = '\0'; 132 133 for (i = 1; i < argc; i++) { 134 char *str = (char *)(long)argv32[i]; 135 if (i != 1) 136 strcat(arcs_cmdline, " "); 137 if (strchr(str, ' ')) { 138 strcat(arcs_cmdline, "\""); 139 strcat(arcs_cmdline, str); 140 strcat(arcs_cmdline, "\""); 141 } else 142 strcat(arcs_cmdline, str); 143 } 144 } 145 146 static int txx9_ic_disable __initdata; 147 static int txx9_dc_disable __initdata; 148 149 #if defined(CONFIG_CPU_TX49XX) 150 /* flush all cache on very early stage (before 4k_cache_init) */ 151 static void __init early_flush_dcache(void) 152 { 153 unsigned int conf = read_c0_config(); 154 unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6)); 155 unsigned int linesz = 32; 156 unsigned long addr, end; 157 158 end = INDEX_BASE + dc_size / 4; 159 /* 4way, waybit=0 */ 160 for (addr = INDEX_BASE; addr < end; addr += linesz) { 161 cache_op(Index_Writeback_Inv_D, addr | 0); 162 cache_op(Index_Writeback_Inv_D, addr | 1); 163 cache_op(Index_Writeback_Inv_D, addr | 2); 164 cache_op(Index_Writeback_Inv_D, addr | 3); 165 } 166 } 167 168 static void __init txx9_cache_fixup(void) 169 { 170 unsigned int conf; 171 172 conf = read_c0_config(); 173 /* flush and disable */ 174 if (txx9_ic_disable) { 175 conf |= TX49_CONF_IC; 176 write_c0_config(conf); 177 } 178 if (txx9_dc_disable) { 179 early_flush_dcache(); 180 conf |= TX49_CONF_DC; 181 write_c0_config(conf); 182 } 183 184 /* enable cache */ 185 conf = read_c0_config(); 186 if (!txx9_ic_disable) 187 conf &= ~TX49_CONF_IC; 188 if (!txx9_dc_disable) 189 conf &= ~TX49_CONF_DC; 190 write_c0_config(conf); 191 192 if (conf & TX49_CONF_IC) 193 pr_info("TX49XX I-Cache disabled.\n"); 194 if (conf & TX49_CONF_DC) 195 pr_info("TX49XX D-Cache disabled.\n"); 196 } 197 #elif defined(CONFIG_CPU_TX39XX) 198 /* flush all cache on very early stage (before tx39_cache_init) */ 199 static void __init early_flush_dcache(void) 200 { 201 unsigned int conf = read_c0_config(); 202 unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >> 203 TX39_CONF_DCS_SHIFT)); 204 unsigned int linesz = 16; 205 unsigned long addr, end; 206 207 end = INDEX_BASE + dc_size / 2; 208 /* 2way, waybit=0 */ 209 for (addr = INDEX_BASE; addr < end; addr += linesz) { 210 cache_op(Index_Writeback_Inv_D, addr | 0); 211 cache_op(Index_Writeback_Inv_D, addr | 1); 212 } 213 } 214 215 static void __init txx9_cache_fixup(void) 216 { 217 unsigned int conf; 218 219 conf = read_c0_config(); 220 /* flush and disable */ 221 if (txx9_ic_disable) { 222 conf &= ~TX39_CONF_ICE; 223 write_c0_config(conf); 224 } 225 if (txx9_dc_disable) { 226 early_flush_dcache(); 227 conf &= ~TX39_CONF_DCE; 228 write_c0_config(conf); 229 } 230 231 /* enable cache */ 232 conf = read_c0_config(); 233 if (!txx9_ic_disable) 234 conf |= TX39_CONF_ICE; 235 if (!txx9_dc_disable) 236 conf |= TX39_CONF_DCE; 237 write_c0_config(conf); 238 239 if (!(conf & TX39_CONF_ICE)) 240 pr_info("TX39XX I-Cache disabled.\n"); 241 if (!(conf & TX39_CONF_DCE)) 242 pr_info("TX39XX D-Cache disabled.\n"); 243 } 244 #else 245 static inline void txx9_cache_fixup(void) 246 { 247 } 248 #endif 249 250 static void __init preprocess_cmdline(void) 251 { 252 static char cmdline[COMMAND_LINE_SIZE] __initdata; 253 char *s; 254 255 strcpy(cmdline, arcs_cmdline); 256 s = cmdline; 257 arcs_cmdline[0] = '\0'; 258 while (s && *s) { 259 char *str = strsep(&s, " "); 260 if (strncmp(str, "board=", 6) == 0) { 261 txx9_board_vec = find_board_byname(str + 6); 262 continue; 263 } else if (strncmp(str, "masterclk=", 10) == 0) { 264 unsigned int val; 265 if (kstrtouint(str + 10, 10, &val) == 0) 266 txx9_master_clock = val; 267 continue; 268 } else if (strcmp(str, "icdisable") == 0) { 269 txx9_ic_disable = 1; 270 continue; 271 } else if (strcmp(str, "dcdisable") == 0) { 272 txx9_dc_disable = 1; 273 continue; 274 } else if (strcmp(str, "toeoff") == 0) { 275 txx9_ccfg_toeon = 0; 276 continue; 277 } else if (strcmp(str, "toeon") == 0) { 278 txx9_ccfg_toeon = 1; 279 continue; 280 } 281 if (arcs_cmdline[0]) 282 strcat(arcs_cmdline, " "); 283 strcat(arcs_cmdline, str); 284 } 285 286 txx9_cache_fixup(); 287 } 288 289 static void __init select_board(void) 290 { 291 const char *envstr; 292 293 /* first, determine by "board=" argument in preprocess_cmdline() */ 294 if (txx9_board_vec) 295 return; 296 /* next, determine by "board" envvar */ 297 envstr = prom_getenv("board"); 298 if (envstr) { 299 txx9_board_vec = find_board_byname(envstr); 300 if (txx9_board_vec) 301 return; 302 } 303 304 /* select "default" board */ 305 #ifdef CONFIG_TOSHIBA_JMR3927 306 txx9_board_vec = &jmr3927_vec; 307 #endif 308 #ifdef CONFIG_CPU_TX49XX 309 switch (TX4938_REV_PCODE()) { 310 #ifdef CONFIG_TOSHIBA_RBTX4927 311 case 0x4927: 312 txx9_board_vec = &rbtx4927_vec; 313 break; 314 case 0x4937: 315 txx9_board_vec = &rbtx4937_vec; 316 break; 317 #endif 318 #ifdef CONFIG_TOSHIBA_RBTX4939 319 case 0x4939: 320 txx9_board_vec = &rbtx4939_vec; 321 break; 322 #endif 323 } 324 #endif 325 } 326 327 void __init prom_init(void) 328 { 329 prom_init_cmdline(); 330 preprocess_cmdline(); 331 select_board(); 332 333 strcpy(txx9_system_type, txx9_board_vec->system); 334 335 txx9_board_vec->prom_init(); 336 } 337 338 const char *get_system_type(void) 339 { 340 return txx9_system_type; 341 } 342 343 const char *__init prom_getenv(const char *name) 344 { 345 const s32 *str; 346 347 if (fw_arg2 < CKSEG0) 348 return NULL; 349 350 str = (const s32 *)fw_arg2; 351 /* YAMON style ("name", "value" pairs) */ 352 while (str[0] && str[1]) { 353 if (!strcmp((const char *)(unsigned long)str[0], name)) 354 return (const char *)(unsigned long)str[1]; 355 str += 2; 356 } 357 return NULL; 358 } 359 360 static void __noreturn txx9_machine_halt(void) 361 { 362 local_irq_disable(); 363 clear_c0_status(ST0_IM); 364 while (1) { 365 if (cpu_wait) { 366 (*cpu_wait)(); 367 if (cpu_has_counter) { 368 /* 369 * Clear counter interrupt while it 370 * breaks WAIT instruction even if 371 * masked. 372 */ 373 write_c0_compare(0); 374 } 375 } 376 } 377 } 378 379 /* Watchdog support */ 380 void __init txx9_wdt_init(unsigned long base) 381 { 382 struct resource res = { 383 .start = base, 384 .end = base + 0x100 - 1, 385 .flags = IORESOURCE_MEM, 386 }; 387 platform_device_register_simple("txx9wdt", -1, &res, 1); 388 } 389 390 void txx9_wdt_now(unsigned long base) 391 { 392 struct txx9_tmr_reg __iomem *tmrptr = 393 ioremap(base, sizeof(struct txx9_tmr_reg)); 394 /* disable watch dog timer */ 395 __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr); 396 __raw_writel(0, &tmrptr->tcr); 397 /* kick watchdog */ 398 __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr); 399 __raw_writel(1, &tmrptr->cpra); /* immediate */ 400 __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG, 401 &tmrptr->tcr); 402 } 403 404 /* SPI support */ 405 void __init txx9_spi_init(int busid, unsigned long base, int irq) 406 { 407 struct resource res[] = { 408 { 409 .start = base, 410 .end = base + 0x20 - 1, 411 .flags = IORESOURCE_MEM, 412 }, { 413 .start = irq, 414 .flags = IORESOURCE_IRQ, 415 }, 416 }; 417 platform_device_register_simple("spi_txx9", busid, 418 res, ARRAY_SIZE(res)); 419 } 420 421 void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr) 422 { 423 struct platform_device *pdev = 424 platform_device_alloc("tc35815-mac", id); 425 if (!pdev || 426 platform_device_add_data(pdev, ethaddr, 6) || 427 platform_device_add(pdev)) 428 platform_device_put(pdev); 429 } 430 431 void __init txx9_sio_init(unsigned long baseaddr, int irq, 432 unsigned int line, unsigned int sclk, int nocts) 433 { 434 #ifdef CONFIG_SERIAL_TXX9 435 struct uart_port req; 436 437 memset(&req, 0, sizeof(req)); 438 req.line = line; 439 req.iotype = UPIO_MEM; 440 req.membase = ioremap(baseaddr, 0x24); 441 req.mapbase = baseaddr; 442 req.irq = irq; 443 if (!nocts) 444 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; 445 if (sclk) { 446 req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/; 447 req.uartclk = sclk; 448 } else 449 req.uartclk = TXX9_IMCLK; 450 early_serial_txx9_setup(&req); 451 #endif /* CONFIG_SERIAL_TXX9 */ 452 } 453 454 #ifdef CONFIG_EARLY_PRINTK 455 static void null_prom_putchar(char c) 456 { 457 } 458 void (*txx9_prom_putchar)(char c) = null_prom_putchar; 459 460 void prom_putchar(char c) 461 { 462 txx9_prom_putchar(c); 463 } 464 465 static void __iomem *early_txx9_sio_port; 466 467 static void early_txx9_sio_putchar(char c) 468 { 469 #define TXX9_SICISR 0x0c 470 #define TXX9_SITFIFO 0x1c 471 #define TXX9_SICISR_TXALS 0x00000002 472 while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) & 473 TXX9_SICISR_TXALS)) 474 ; 475 __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO); 476 } 477 478 void __init txx9_sio_putchar_init(unsigned long baseaddr) 479 { 480 early_txx9_sio_port = ioremap(baseaddr, 0x24); 481 txx9_prom_putchar = early_txx9_sio_putchar; 482 } 483 #endif /* CONFIG_EARLY_PRINTK */ 484 485 /* wrappers */ 486 void __init plat_mem_setup(void) 487 { 488 ioport_resource.start = 0; 489 ioport_resource.end = ~0UL; /* no limit */ 490 iomem_resource.start = 0; 491 iomem_resource.end = ~0UL; /* no limit */ 492 493 /* fallback restart/halt routines */ 494 _machine_restart = (void (*)(char *))txx9_machine_halt; 495 _machine_halt = txx9_machine_halt; 496 pm_power_off = txx9_machine_halt; 497 498 #ifdef CONFIG_PCI 499 pcibios_plat_setup = txx9_pcibios_setup; 500 #endif 501 txx9_board_vec->mem_setup(); 502 } 503 504 void __init arch_init_irq(void) 505 { 506 txx9_board_vec->irq_setup(); 507 } 508 509 void __init plat_time_init(void) 510 { 511 #ifdef CONFIG_CPU_TX49XX 512 mips_hpt_frequency = txx9_cpu_clock / 2; 513 #endif 514 txx9_board_vec->time_init(); 515 } 516 517 static void txx9_clk_init(void) 518 { 519 struct clk_hw *hw; 520 int error; 521 522 hw = clk_hw_register_fixed_rate(NULL, "gbus", NULL, 0, txx9_gbus_clock); 523 if (IS_ERR(hw)) { 524 error = PTR_ERR(hw); 525 goto fail; 526 } 527 528 hw = clk_hw_register_fixed_factor(NULL, "imbus", "gbus", 0, 1, 2); 529 error = clk_hw_register_clkdev(hw, "imbus_clk", NULL); 530 if (error) 531 goto fail; 532 533 #ifdef CONFIG_CPU_TX49XX 534 if (TX4938_REV_PCODE() == 0x4938) { 535 hw = clk_hw_register_fixed_factor(NULL, "spi", "gbus", 0, 1, 4); 536 error = clk_hw_register_clkdev(hw, "spi-baseclk", NULL); 537 if (error) 538 goto fail; 539 } 540 #endif 541 542 return; 543 544 fail: 545 pr_err("Failed to register clocks: %d\n", error); 546 } 547 548 static int __init _txx9_arch_init(void) 549 { 550 txx9_clk_init(); 551 552 if (txx9_board_vec->arch_init) 553 txx9_board_vec->arch_init(); 554 return 0; 555 } 556 arch_initcall(_txx9_arch_init); 557 558 static int __init _txx9_device_init(void) 559 { 560 if (txx9_board_vec->device_init) 561 txx9_board_vec->device_init(); 562 return 0; 563 } 564 device_initcall(_txx9_device_init); 565 566 int (*txx9_irq_dispatch)(int pending); 567 asmlinkage void plat_irq_dispatch(void) 568 { 569 int pending = read_c0_status() & read_c0_cause() & ST0_IM; 570 int irq = txx9_irq_dispatch(pending); 571 572 if (likely(irq >= 0)) 573 do_IRQ(irq); 574 else 575 spurious_interrupt(); 576 } 577 578 /* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */ 579 #ifdef NEEDS_TXX9_SWIZZLE_ADDR_B 580 static unsigned long __swizzle_addr_none(unsigned long port) 581 { 582 return port; 583 } 584 unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none; 585 EXPORT_SYMBOL(__swizzle_addr_b); 586 #endif 587 588 #ifdef NEEDS_TXX9_IOSWABW 589 static u16 ioswabw_default(volatile u16 *a, u16 x) 590 { 591 return le16_to_cpu(x); 592 } 593 static u16 __mem_ioswabw_default(volatile u16 *a, u16 x) 594 { 595 return x; 596 } 597 u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default; 598 EXPORT_SYMBOL(ioswabw); 599 u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default; 600 EXPORT_SYMBOL(__mem_ioswabw); 601 #endif 602 603 void __init txx9_physmap_flash_init(int no, unsigned long addr, 604 unsigned long size, 605 const struct physmap_flash_data *pdata) 606 { 607 #if IS_ENABLED(CONFIG_MTD_PHYSMAP) 608 struct resource res = { 609 .start = addr, 610 .end = addr + size - 1, 611 .flags = IORESOURCE_MEM, 612 }; 613 struct platform_device *pdev; 614 static struct mtd_partition parts[2]; 615 struct physmap_flash_data pdata_part; 616 617 /* If this area contained boot area, make separate partition */ 618 if (pdata->nr_parts == 0 && !pdata->parts && 619 addr < 0x1fc00000 && addr + size > 0x1fc00000 && 620 !parts[0].name) { 621 parts[0].name = "boot"; 622 parts[0].offset = 0x1fc00000 - addr; 623 parts[0].size = addr + size - 0x1fc00000; 624 parts[1].name = "user"; 625 parts[1].offset = 0; 626 parts[1].size = 0x1fc00000 - addr; 627 pdata_part = *pdata; 628 pdata_part.nr_parts = ARRAY_SIZE(parts); 629 pdata_part.parts = parts; 630 pdata = &pdata_part; 631 } 632 633 pdev = platform_device_alloc("physmap-flash", no); 634 if (!pdev || 635 platform_device_add_resources(pdev, &res, 1) || 636 platform_device_add_data(pdev, pdata, sizeof(*pdata)) || 637 platform_device_add(pdev)) 638 platform_device_put(pdev); 639 #endif 640 } 641 642 void __init txx9_ndfmc_init(unsigned long baseaddr, 643 const struct txx9ndfmc_platform_data *pdata) 644 { 645 #if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC) 646 struct resource res = { 647 .start = baseaddr, 648 .end = baseaddr + 0x1000 - 1, 649 .flags = IORESOURCE_MEM, 650 }; 651 struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1); 652 653 if (!pdev || 654 platform_device_add_resources(pdev, &res, 1) || 655 platform_device_add_data(pdev, pdata, sizeof(*pdata)) || 656 platform_device_add(pdev)) 657 platform_device_put(pdev); 658 #endif 659 } 660 661 #if IS_ENABLED(CONFIG_LEDS_GPIO) 662 static DEFINE_SPINLOCK(txx9_iocled_lock); 663 664 #define TXX9_IOCLED_MAXLEDS 8 665 666 struct txx9_iocled_data { 667 struct gpio_chip chip; 668 u8 cur_val; 669 void __iomem *mmioaddr; 670 struct gpio_led_platform_data pdata; 671 struct gpio_led leds[TXX9_IOCLED_MAXLEDS]; 672 char names[TXX9_IOCLED_MAXLEDS][32]; 673 }; 674 675 static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset) 676 { 677 struct txx9_iocled_data *data = gpiochip_get_data(chip); 678 return !!(data->cur_val & (1 << offset)); 679 } 680 681 static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset, 682 int value) 683 { 684 struct txx9_iocled_data *data = gpiochip_get_data(chip); 685 unsigned long flags; 686 spin_lock_irqsave(&txx9_iocled_lock, flags); 687 if (value) 688 data->cur_val |= 1 << offset; 689 else 690 data->cur_val &= ~(1 << offset); 691 writeb(data->cur_val, data->mmioaddr); 692 mmiowb(); 693 spin_unlock_irqrestore(&txx9_iocled_lock, flags); 694 } 695 696 static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset) 697 { 698 return 0; 699 } 700 701 static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset, 702 int value) 703 { 704 txx9_iocled_set(chip, offset, value); 705 return 0; 706 } 707 708 void __init txx9_iocled_init(unsigned long baseaddr, 709 int basenum, unsigned int num, int lowactive, 710 const char *color, char **deftriggers) 711 { 712 struct txx9_iocled_data *iocled; 713 struct platform_device *pdev; 714 int i; 715 static char *default_triggers[] __initdata = { 716 "heartbeat", 717 "disk-activity", 718 "nand-disk", 719 NULL, 720 }; 721 722 if (!deftriggers) 723 deftriggers = default_triggers; 724 iocled = kzalloc(sizeof(*iocled), GFP_KERNEL); 725 if (!iocled) 726 return; 727 iocled->mmioaddr = ioremap(baseaddr, 1); 728 if (!iocled->mmioaddr) 729 goto out_free; 730 iocled->chip.get = txx9_iocled_get; 731 iocled->chip.set = txx9_iocled_set; 732 iocled->chip.direction_input = txx9_iocled_dir_in; 733 iocled->chip.direction_output = txx9_iocled_dir_out; 734 iocled->chip.label = "iocled"; 735 iocled->chip.base = basenum; 736 iocled->chip.ngpio = num; 737 if (gpiochip_add_data(&iocled->chip, iocled)) 738 goto out_unmap; 739 if (basenum < 0) 740 basenum = iocled->chip.base; 741 742 pdev = platform_device_alloc("leds-gpio", basenum); 743 if (!pdev) 744 goto out_gpio; 745 iocled->pdata.num_leds = num; 746 iocled->pdata.leds = iocled->leds; 747 for (i = 0; i < num; i++) { 748 struct gpio_led *led = &iocled->leds[i]; 749 snprintf(iocled->names[i], sizeof(iocled->names[i]), 750 "iocled:%s:%u", color, i); 751 led->name = iocled->names[i]; 752 led->gpio = basenum + i; 753 led->active_low = lowactive; 754 if (deftriggers && *deftriggers) 755 led->default_trigger = *deftriggers++; 756 } 757 pdev->dev.platform_data = &iocled->pdata; 758 if (platform_device_add(pdev)) 759 goto out_pdev; 760 return; 761 762 out_pdev: 763 platform_device_put(pdev); 764 out_gpio: 765 gpiochip_remove(&iocled->chip); 766 out_unmap: 767 iounmap(iocled->mmioaddr); 768 out_free: 769 kfree(iocled); 770 } 771 #else /* CONFIG_LEDS_GPIO */ 772 void __init txx9_iocled_init(unsigned long baseaddr, 773 int basenum, unsigned int num, int lowactive, 774 const char *color, char **deftriggers) 775 { 776 } 777 #endif /* CONFIG_LEDS_GPIO */ 778 779 void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq, 780 const struct txx9dmac_platform_data *pdata) 781 { 782 #if IS_ENABLED(CONFIG_TXX9_DMAC) 783 struct resource res[] = { 784 { 785 .start = baseaddr, 786 .end = baseaddr + 0x800 - 1, 787 .flags = IORESOURCE_MEM, 788 #ifndef CONFIG_MACH_TX49XX 789 }, { 790 .start = irq, 791 .flags = IORESOURCE_IRQ, 792 #endif 793 } 794 }; 795 #ifdef CONFIG_MACH_TX49XX 796 struct resource chan_res[] = { 797 { 798 .flags = IORESOURCE_IRQ, 799 } 800 }; 801 #endif 802 struct platform_device *pdev = platform_device_alloc("txx9dmac", id); 803 struct txx9dmac_chan_platform_data cpdata; 804 int i; 805 806 if (!pdev || 807 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) || 808 platform_device_add_data(pdev, pdata, sizeof(*pdata)) || 809 platform_device_add(pdev)) { 810 platform_device_put(pdev); 811 return; 812 } 813 memset(&cpdata, 0, sizeof(cpdata)); 814 cpdata.dmac_dev = pdev; 815 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) { 816 #ifdef CONFIG_MACH_TX49XX 817 chan_res[0].start = irq + i; 818 #endif 819 pdev = platform_device_alloc("txx9dmac-chan", 820 id * TXX9_DMA_MAX_NR_CHANNELS + i); 821 if (!pdev || 822 #ifdef CONFIG_MACH_TX49XX 823 platform_device_add_resources(pdev, chan_res, 824 ARRAY_SIZE(chan_res)) || 825 #endif 826 platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) || 827 platform_device_add(pdev)) 828 platform_device_put(pdev); 829 } 830 #endif 831 } 832 833 void __init txx9_aclc_init(unsigned long baseaddr, int irq, 834 unsigned int dmac_id, 835 unsigned int dma_chan_out, 836 unsigned int dma_chan_in) 837 { 838 } 839 840 static struct bus_type txx9_sramc_subsys = { 841 .name = "txx9_sram", 842 .dev_name = "txx9_sram", 843 }; 844 845 struct txx9_sramc_dev { 846 struct device dev; 847 struct bin_attribute bindata_attr; 848 void __iomem *base; 849 }; 850 851 static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj, 852 struct bin_attribute *bin_attr, 853 char *buf, loff_t pos, size_t size) 854 { 855 struct txx9_sramc_dev *dev = bin_attr->private; 856 size_t ramsize = bin_attr->size; 857 858 if (pos >= ramsize) 859 return 0; 860 if (pos + size > ramsize) 861 size = ramsize - pos; 862 memcpy_fromio(buf, dev->base + pos, size); 863 return size; 864 } 865 866 static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj, 867 struct bin_attribute *bin_attr, 868 char *buf, loff_t pos, size_t size) 869 { 870 struct txx9_sramc_dev *dev = bin_attr->private; 871 size_t ramsize = bin_attr->size; 872 873 if (pos >= ramsize) 874 return 0; 875 if (pos + size > ramsize) 876 size = ramsize - pos; 877 memcpy_toio(dev->base + pos, buf, size); 878 return size; 879 } 880 881 static void txx9_device_release(struct device *dev) 882 { 883 struct txx9_sramc_dev *tdev; 884 885 tdev = container_of(dev, struct txx9_sramc_dev, dev); 886 kfree(tdev); 887 } 888 889 void __init txx9_sramc_init(struct resource *r) 890 { 891 struct txx9_sramc_dev *dev; 892 size_t size; 893 int err; 894 895 err = subsys_system_register(&txx9_sramc_subsys, NULL); 896 if (err) 897 return; 898 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 899 if (!dev) 900 return; 901 size = resource_size(r); 902 dev->base = ioremap(r->start, size); 903 if (!dev->base) { 904 kfree(dev); 905 return; 906 } 907 dev->dev.release = &txx9_device_release; 908 dev->dev.bus = &txx9_sramc_subsys; 909 sysfs_bin_attr_init(&dev->bindata_attr); 910 dev->bindata_attr.attr.name = "bindata"; 911 dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR; 912 dev->bindata_attr.read = txx9_sram_read; 913 dev->bindata_attr.write = txx9_sram_write; 914 dev->bindata_attr.size = size; 915 dev->bindata_attr.private = dev; 916 err = device_register(&dev->dev); 917 if (err) 918 goto exit_put; 919 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr); 920 if (err) { 921 iounmap(dev->base); 922 device_unregister(&dev->dev); 923 } 924 return; 925 exit_put: 926 iounmap(dev->base); 927 put_device(&dev->dev); 928 } 929