1 #include <linux/types.h> 2 #include <linux/interrupt.h> 3 #include <linux/time.h> 4 5 #include <asm/i8253.h> 6 #include <asm/sni.h> 7 #include <asm/time.h> 8 #include <asm-generic/rtc.h> 9 10 #define SNI_CLOCK_TICK_RATE 3686400 11 #define SNI_COUNTER2_DIV 64 12 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) 13 14 static void sni_a20r_timer_ack(void) 15 { 16 *(volatile u8 *)A20R_PT_TIM0_ACK = 0x0; wmb(); 17 } 18 19 /* 20 * a20r platform uses 2 counters to divide the input frequency. 21 * Counter 2 output is connected to Counter 0 & 1 input. 22 */ 23 static void __init sni_a20r_timer_setup(struct irqaction *irq) 24 { 25 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; wmb(); 26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV) & 0xff; wmb(); 27 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV >> 8) & 0xff; wmb(); 28 29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; wmb(); 30 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV) & 0xff; wmb(); 31 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV >> 8) & 0xff; wmb(); 32 33 setup_irq(SNI_A20R_IRQ_TIMER, irq); 34 mips_timer_ack = sni_a20r_timer_ack; 35 } 36 37 #define SNI_8254_TICK_RATE 1193182UL 38 39 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255) 40 41 static __init unsigned long dosample(void) 42 { 43 u32 ct0, ct1; 44 volatile u8 msb, lsb; 45 46 /* Start the counter. */ 47 outb_p(0x34, 0x43); 48 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 49 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 50 51 /* Get initial counter invariant */ 52 ct0 = read_c0_count(); 53 54 /* Latch and spin until top byte of counter0 is zero */ 55 do { 56 outb(0x00, 0x43); 57 lsb = inb(0x40); 58 msb = inb(0x40); 59 ct1 = read_c0_count(); 60 } while (msb); 61 62 /* Stop the counter. */ 63 outb(0x38, 0x43); 64 /* 65 * Return the difference, this is how far the r4k counter increments 66 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 67 * clock (= 1000000 / HZ / 2). 68 */ 69 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/ 70 return (ct1 - ct0) / (500000/HZ) * (500000/HZ); 71 } 72 73 /* 74 * Here we need to calibrate the cycle counter to at least be close. 75 */ 76 void __init plat_time_init(void) 77 { 78 unsigned long r4k_ticks[3]; 79 unsigned long r4k_tick; 80 81 /* 82 * Figure out the r4k offset, the algorithm is very simple and works in 83 * _all_ cases as long as the 8254 counter register itself works ok (as 84 * an interrupt driving timer it does not because of bug, this is why 85 * we are using the onchip r4k counter/compare register to serve this 86 * purpose, but for r4k_offset calculation it will work ok for us). 87 * There are other very complicated ways of performing this calculation 88 * but this one works just fine so I am not going to futz around. ;-) 89 */ 90 printk(KERN_INFO "Calibrating system timer... "); 91 dosample(); /* Prime cache. */ 92 dosample(); /* Prime cache. */ 93 /* Zero is NOT an option. */ 94 do { 95 r4k_ticks[0] = dosample(); 96 } while (!r4k_ticks[0]); 97 do { 98 r4k_ticks[1] = dosample(); 99 } while (!r4k_ticks[1]); 100 101 if (r4k_ticks[0] != r4k_ticks[1]) { 102 printk("warning: timer counts differ, retrying... "); 103 r4k_ticks[2] = dosample(); 104 if (r4k_ticks[2] == r4k_ticks[0] 105 || r4k_ticks[2] == r4k_ticks[1]) 106 r4k_tick = r4k_ticks[2]; 107 else { 108 printk("disagreement, using average... "); 109 r4k_tick = (r4k_ticks[0] + r4k_ticks[1] 110 + r4k_ticks[2]) / 3; 111 } 112 } else 113 r4k_tick = r4k_ticks[0]; 114 115 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, 116 (int) (r4k_tick / (500000 / HZ)), 117 (int) (r4k_tick % (500000 / HZ))); 118 119 mips_hpt_frequency = r4k_tick * HZ; 120 121 setup_pit_timer(); 122 } 123 124 /* 125 * R4k counter based timer interrupt. Works on RM200-225 and possibly 126 * others but not on RM400 127 */ 128 static void __init sni_cpu_timer_setup(struct irqaction *irq) 129 { 130 setup_irq(SNI_MIPS_IRQ_CPU_TIMER, irq); 131 } 132 133 void __init plat_timer_setup(struct irqaction *irq) 134 { 135 switch (sni_brd_type) { 136 case SNI_BRD_10: 137 case SNI_BRD_10NEW: 138 case SNI_BRD_TOWER_OASIC: 139 case SNI_BRD_MINITOWER: 140 sni_a20r_timer_setup(irq); 141 break; 142 143 case SNI_BRD_PCI_TOWER: 144 case SNI_BRD_RM200: 145 case SNI_BRD_PCI_MTOWER: 146 case SNI_BRD_PCI_DESKTOP: 147 case SNI_BRD_PCI_TOWER_CPLUS: 148 case SNI_BRD_PCI_MTOWER_CPLUS: 149 sni_cpu_timer_setup(irq); 150 break; 151 } 152 } 153 154 unsigned long read_persistent_clock(void) 155 { 156 return -1; 157 } 158