1 /* 2 * Setup pointers to hardware-dependent routines. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org) 9 */ 10 #include <linux/config.h> 11 #include <linux/eisa.h> 12 #include <linux/hdreg.h> 13 #include <linux/ioport.h> 14 #include <linux/sched.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/mc146818rtc.h> 18 #include <linux/pm.h> 19 #include <linux/pci.h> 20 #include <linux/console.h> 21 #include <linux/fb.h> 22 #include <linux/tty.h> 23 24 #include <asm/arc/types.h> 25 #include <asm/sgialib.h> 26 #include <asm/bcache.h> 27 #include <asm/bootinfo.h> 28 #include <asm/io.h> 29 #include <asm/irq.h> 30 #include <asm/mc146818-time.h> 31 #include <asm/processor.h> 32 #include <asm/ptrace.h> 33 #include <asm/reboot.h> 34 #include <asm/sni.h> 35 #include <asm/time.h> 36 #include <asm/traps.h> 37 38 extern void sni_machine_restart(char *command); 39 extern void sni_machine_halt(void); 40 extern void sni_machine_power_off(void); 41 42 static void __init sni_rm200_pci_timer_setup(struct irqaction *irq) 43 { 44 /* set the clock to 100 Hz */ 45 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ 46 outb_p(LATCH & 0xff , 0x40); /* LSB */ 47 outb(LATCH >> 8 , 0x40); /* MSB */ 48 setup_irq(0, irq); 49 } 50 51 /* 52 * A bit more gossip about the iron we're running on ... 53 */ 54 static inline void sni_pcimt_detect(void) 55 { 56 char boardtype[80]; 57 unsigned char csmsr; 58 char *p = boardtype; 59 unsigned int asic; 60 61 csmsr = *(volatile unsigned char *)PCIMT_CSMSR; 62 63 p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300"); 64 if ((csmsr & 0x80) == 0) 65 p += sprintf(p, ", board revision %s", 66 (csmsr & 0x20) ? "D" : "C"); 67 asic = csmsr & 0x80; 68 asic = (csmsr & 0x08) ? asic : !asic; 69 p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1"); 70 printk("%s.\n", boardtype); 71 } 72 73 static void __init sni_display_setup(void) 74 { 75 #ifdef CONFIG_VT 76 #if defined(CONFIG_VGA_CONSOLE) 77 struct screen_info *si = &screen_info; 78 DISPLAY_STATUS *di; 79 80 di = ArcGetDisplayStatus(1); 81 82 if (di) { 83 si->orig_x = di->CursorXPosition; 84 si->orig_y = di->CursorYPosition; 85 si->orig_video_cols = di->CursorMaxXPosition; 86 si->orig_video_lines = di->CursorMaxYPosition; 87 si->orig_video_isVGA = VIDEO_TYPE_VGAC; 88 si->orig_video_points = 16; 89 } 90 #endif 91 #endif 92 } 93 94 static struct resource sni_io_resource = { 95 "PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO, 96 }; 97 98 static struct resource pcimt_io_resources[] = { 99 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, 100 { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, 101 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY }, 102 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, 103 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, 104 { "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY } 105 }; 106 107 static struct resource sni_mem_resource = { 108 "PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM 109 }; 110 111 /* 112 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used 113 * for other purposes. Be paranoid and allocate all of the before the PCI 114 * code gets a chance to to map anything else there ... 115 * 116 * This leaves the following areas available: 117 * 118 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory 119 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory 120 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory 121 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory 122 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory 123 */ 124 static struct resource pcimt_mem_resources[] = { 125 { "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY }, 126 { "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY }, 127 { "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY }, 128 { "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY}, 129 { "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY }, 130 { "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY}, 131 { "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY}, 132 { "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY}, 133 { "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY}, 134 { "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY}, 135 { "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY}, 136 { "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY}, 137 { "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY} 138 }; 139 140 static void __init sni_resource_init(void) 141 { 142 int i; 143 144 /* request I/O space for devices used on all i[345]86 PCs */ 145 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) 146 request_resource(&ioport_resource, pcimt_io_resources + i); 147 148 /* request mem space for pcimt-specific devices */ 149 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++) 150 request_resource(&sni_mem_resource, pcimt_mem_resources + i); 151 152 ioport_resource.end = sni_io_resource.end; 153 } 154 155 extern struct pci_ops sni_pci_ops; 156 157 static struct pci_controller sni_controller = { 158 .pci_ops = &sni_pci_ops, 159 .mem_resource = &sni_mem_resource, 160 .mem_offset = 0x10000000UL, 161 .io_resource = &sni_io_resource, 162 .io_offset = 0x00000000UL 163 }; 164 165 static inline void sni_pcimt_time_init(void) 166 { 167 rtc_mips_get_time = mc146818_get_cmos_time; 168 rtc_mips_set_time = mc146818_set_rtc_mmss; 169 } 170 171 void __init plat_setup(void) 172 { 173 sni_pcimt_detect(); 174 sni_pcimt_sc_init(); 175 sni_pcimt_time_init(); 176 177 set_io_port_base(SNI_PORT_BASE); 178 ioport_resource.end = sni_io_resource.end; 179 180 /* 181 * Setup (E)ISA I/O memory access stuff 182 */ 183 isa_slot_offset = 0xb0000000; 184 #ifdef CONFIG_EISA 185 EISA_bus = 1; 186 #endif 187 188 sni_resource_init(); 189 board_timer_setup = sni_rm200_pci_timer_setup; 190 191 _machine_restart = sni_machine_restart; 192 _machine_halt = sni_machine_halt; 193 pm_power_off = sni_machine_power_off; 194 195 sni_display_setup(); 196 197 #ifdef CONFIG_PCI 198 register_pci_controller(&sni_controller); 199 #endif 200 } 201